Re: [RESEND PATCH V5 1/2] perf/core: Add new branch sample type for HW index of raw branch records

Peter Zijlstra
2020-01-20T09:23:13Z

On Thu, Jan 16, 2020 at 07:57:56AM -0800, kan.liang@linux.intel.com wrote:

> struct perf_branch_stack {
> __u64 nr;
> + __u64 hw_idx;
> struct perf_branch_entry entries[0];
> };

The above and below order doesn't match.

> @@ -849,7 +853,11 @@ enum perf_event_type {
> * char data[size];}&& PERF_SAMPLE_RAW
> *
> * { u64 nr;
> - * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
> + * { u64 from, to, flags } lbr[nr];
> + *
> + * # only available if PERF_SAMPLE_BRANCH_HW_INDEX is set
> + * u64 hw_idx;
> + * } && PERF_SAMPLE_BRANCH_STACK

That wants to be written as:

{ u64 nr;
{ u64 from, to, flags; } entries[nr];
{ u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
} && PERF_SAMPLE_BRANCH_STACK

But the big question is; why isn't it:

{ u64 nr;
{ u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
{ u64 from, to, flags; } entries[nr];
} && PERF_SAMPLE_BRANCH_STACK

to match the struct perf_branch_stack order. Having that variable sized
entry in the middle just seems weird.

> *
> * { u64 abi; # enum perf_sample_regs_abi
> * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER