From: Alexander Stein <alexander.stein@systec-electronic.com>
To: linux-kernel@vger.kernel.org
Cc: Minghuan Lian <Minghuan.Lian@nxp.com>,
linux-arm-kernel@lists.infradead.org,
Marc Zyngier <marc.zyngier@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>, Roy Zang <roy.zang@nxp.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
Stuart Yoder <stuart.yoder@nxp.com>,
Yang-Leo Li <leoyang.li@nxp.com>
Subject: Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support
Date: Wed, 23 Mar 2016 10:18:11 +0100 [thread overview]
Message-ID: <7239962.9Fyo0vfqsc@ws-stein> (raw)
In-Reply-To: <1457321782-3245-2-git-send-email-Minghuan.Lian@nxp.com>
On Monday 07 March 2016 11:36:22, Minghuan Lian wrote:
> Some kind of NXP Layerscape SoC provides a MSI
> implementation which uses two SCFG registers MSIIR and
> MSIR to support 32 MSI interrupts for each PCIe controller.
> The patch is to support it.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit strange though:
> grep eth3 /proc/interrupts
>
> 63: 49 0 MSI 134742016 Edge eth3-rx-0
> 64: 3 0 MSI 134742017 Edge eth3-tx-0
> 65: 4 0 MSI 134742018 Edge eth3
Best regards,
Alexander
next prev parent reply other threads:[~2016-03-23 9:18 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 3:36 [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI Minghuan Lian
2016-03-07 3:36 ` [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support Minghuan Lian
2016-03-07 9:50 ` Marc Zyngier
2016-04-22 5:33 ` Leo Li
2016-04-22 7:43 ` Marc Zyngier
2016-04-22 7:53 ` Minghuan Lian
2016-04-22 7:58 ` Marc Zyngier
2016-03-23 9:18 ` Alexander Stein [this message]
2016-03-23 10:50 ` Minghuan Lian
2016-03-23 11:08 ` Marc Zyngier
2016-03-23 11:19 ` Alexander Stein
2016-03-23 11:36 ` Marc Zyngier
2016-03-09 8:57 ` [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI Minghuan Lian
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7239962.9Fyo0vfqsc@ws-stein \
--to=alexander.stein@systec-electronic.com \
--cc=Minghuan.Lian@nxp.com \
--cc=jason@lakedaemon.net \
--cc=leoyang.li@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=mingkai.hu@nxp.com \
--cc=roy.zang@nxp.com \
--cc=stuart.yoder@nxp.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox