From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423584AbcBQQ7W (ORCPT ); Wed, 17 Feb 2016 11:59:22 -0500 Received: from mout.kundenserver.de ([217.72.192.73]:55437 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030335AbcBQQ7U (ORCPT ); Wed, 17 Feb 2016 11:59:20 -0500 From: Arnd Bergmann To: Vladimir Murzin Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, andy.shevchenko@gmail.com, galak@codeaurora.org, linux-serial@vger.kernel.org, u.kleine-koenig@pengutronix.de, tglx@linutronix.de, linux-api@vger.kernel.org, jslaby@suse.cz, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 09/10] ARM: dts: introduce MPS2 AN385/AN386 Date: Wed, 17 Feb 2016 17:58:09 +0100 Message-ID: <7272921.u1gphgWzUn@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <56C4A46C.50506@arm.com> References: <1455617295-23736-1-git-send-email-vladimir.murzin@arm.com> <56C349E6.2000002@arm.com> <56C4A46C.50506@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:K4j3K/GAZSnIGURmbIorVNDABbaaTf9B6bMzLU0hDfrKGiZL6cS yKo7+Opq1U/0n2iDz+PCQrLZquq/o8MGHsLcVScINGcdPj5UPWV408eSyVuU15f+prnLlV1 7MZsqSxbFLwLAKrBg0Kcm+0aOqtYR5i8XYSZLtfiv384lFgZDyH6+hgWZ/hkMBQzyair0EW UpGXL+4xecAYzI93OEswA== X-UI-Out-Filterresults: notjunk:1;V01:K0:NczhbtVldLs=:sY0uFLLb9eZrUYwkOCZETG GT/eE4AaYkTpBycbJY0LBsRJIpkKv9QNz92f6F6ODmsZXusQcyESoPItucSP0wzxwe0p/13xs f/c3ixH15emPX93eYrelv05/UPS62h5seKbsHikOJd0lW6YrbE/1xZ3s4gu+NeI8cxvHjewE5 1M8hn53xpsEgQrsT2N6yKs5a77R9ByBIzZ+pdrdwcCOOhBxJp+sBoAasq/FR4ALaTnuTVPOc4 5gd7Z0oX9Obbd1Ub89UVoM4B2NAixwux6UsG1cGWst+kmShFCW7zaKCXUYLCH6v2yy3KaElVa QusVVhE3ISojacwJcdBqxK3+2yK6yO+wF1zimAL+r1PwhZZjx9j95j4YIKdOklg4vajSy7Q/i FeUr1UGiY08cwe4T7O/7A9+S3+F6oWOWThtxGjYbcD8iVgp72p+IpHj42/sgCydYiO4/4UZxO Rfie8AylNZ4AbHv5ie78yS1ZN5yzgDHKTlwCp/RVzoisTELD/xSdZ/OLaV+UV5dygMWdYjupH 2mfaJ3DDYCS8/ytF5DMzQfNJRULMG4h78hiHoZWXKAvhN30D0A/u7ovEqRJYTsJz27tucdhdf Qziw4NJNPPgun/MYbFHv8aEW8uq8nxNT0xBu8aKxT3AYPbBECskEJbQvdedpC6kEOHGu/5iZg 6+N/0L4N84vjYQWVzc/uvfxPsgNGfIq0Z7mJiLEPfLHLLZ89j7LdX1kSfTNmxxX9QT6XVyS+s GxcZSKAgC2Av1LG3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday 17 February 2016 16:48:44 Vladimir Murzin wrote: > On 16/02/16 16:10, Vladimir Murzin wrote: > > On 16/02/16 11:01, Arnd Bergmann wrote: > >> On Tuesday 16 February 2016 10:08:14 Vladimir Murzin wrote: > >>> + > >>> + ethernet@40200000 { > >>> + compatible = "smsc,lan9220", "smsc,lan9115"; > >>> + reg = <0x40200000 0x10000>; > >>> + interrupts = <13>; > >>> + interrupt-parent = <&nvic>; > >>> + smsc,irq-active-high; > >>> + }; > >>> +}; > >>> + > >>> > >> > >> This node seems slightly misplaced. Is there some external bus interface > >> that this is connected to? The address suggests that it should be somewhere > >> below the /soc node, and you probably want to list the external bus > >> interface with a "ranges" property that identifies the addresses visibile > >> there, and put the external chip under there. > >> > > > > I might messed it up since the MAC/PHY connects to the same 16-bit > > interface as the 16MB PSRAM external memory and both connected via AHB. > > > > Not sure how it should be expressed, so some help form DT camp would be > > appreciated. > > Does following fixup address your point on where/how ethernet node > should be placed? > diff --git a/arch/arm/boot/dts/mps2-an385.dts b/arch/arm/boot/dts/an385.dts > index 976f86d..50c8d24 100644 > --- a/arch/arm/boot/dts/mps2-an385.dts > +++ b/arch/arm/boot/dts/mps2-an385.dts > @@ -63,14 +63,10 @@ > device_type = "memory"; > reg = <0x21000000 0x1000000>; > }; > +}; > > - ethernet@40200000 { > - compatible = "smsc,lan9220", "smsc,lan9115"; > - reg = <0x40200000 0x10000>; > - interrupts = <13>; > - interrupt-parent = <&nvic>; > - smsc,irq-active-high; > - }; > +&mb { > + ranges = <0 0x40200000 0x10000>; > }; How is the range being set here? The way I read this is: "There is an external bus controller whose single CPU physical address for MMIO is configurable. The chip always connects a lan9220 device to it (as that is in the dtsi file) and nothing else is possible, and the bootloader in this version of the machine has configured the window to be at address 0x40200000." Is that what the hardware does? I would have expected the opposite, with the external bus interface being hardwired to one or more physical addresses (more than one if you have multiple chip-selects), and then allow to connect different devices, which are in the .dts file, while the bus controller is defined in the .dtsi file. Arnd