Re: [PATCH v5 char-misc-next] misc: microchip: pci1xxxx: Add OTP/EEPROM driver for the pci1xxxx switch

[Michael Walle <michael@walle.cc>]

Hi,

>> > Microchip's pci1xxxx is an unmanaged PCIe3.1a switch for consumer,
>> > industrial, and automotive applications. This switch integrates OTP
>> > and EEPROM to enable customization of the part in the field. This
>> > patch provides the OTP/EEPROM driver to support the same.
>> 
>> Why isn't this driver using the nvmem subsystem which is usually used 
>> for
>> OTP and EEPROM?
> Michael, these OTP and EEPROM memories do not have any fixed location
> registers which
> store values (Eg. mac address, config parameters, etc) at fixed 
> offsets.
> It stores a bunch of records, each of which has some data to be
> written into the device's
> hardware registers at different locations. These records are directly
> consumed by the hardware
> and interpreted without the involvement of the software.
> Therefore, we don't require any OTP / EEPROM register map to be input
> to the OS / driver through
> device tree or board files.
> I only had to enumerate two separate block devices using the driver so
> that the config binary files can be
> overlayed using the dd command.
> Since this is not fitting like a conventional nvme device, I didn't
> choose the nvme subsystem.
> Please let me know your thoughts / comments if any.

So this is only for provisioning. i.e. during manufacturing a board
which uses this PCI bridge? There are no kernel users, nor is
there a common interface towards user-space. But just some block
device (why not a char device?) exposed to userspace. I presume
there is a companion userspace application for it? Why do you take
the extra step and have a (random) kernel interface, you could
also just access the PCI device directly from userspace within your
companion application, e.g. through libpci.

Just my two cents. I guess it's up to you and Greg who has to
maintain it.

-michael