From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4341AC4167B for ; Mon, 27 Nov 2023 23:41:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233708AbjK0XlW (ORCPT ); Mon, 27 Nov 2023 18:41:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231359AbjK0XlU (ORCPT ); Mon, 27 Nov 2023 18:41:20 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 407B81B1 for ; Mon, 27 Nov 2023 15:41:27 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 75224C433C8; Mon, 27 Nov 2023 23:41:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701128486; bh=weP+2DgJBx1dYZy08M9yhRAGupDOCwbQuosE0EUyWV8=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=a7rXnkcZC0eEvflSMXIq1b0VcYoXkkWXq7OxnUI3DSeFDFGx+J/xGScO0HjQZfmMe LqYpPyoLGy2r+5CHC6aiamz5sN4VcghqVZvgYwctTYV2gTK3RlcyemaLO7XVfCZdsX e3faqKi6gg4r+yKlUMjZuo08wMW7AOwvfxjpa7z1LkXR1SHAXT9mMf6mgHJwCm6coh QTIrRv6awIasaqIatl+jqQiP9RYv+ySszOgyI6ZbeIO1Mnhlv2H7PLeR/tv9Duq0Eh h3P7/evhc5HEy5y1At1XjPkCfXOXXdN7Prv/qJh6g7aig9avY2WHIRtOKGnTZvfr4g HHOsRFJNAYLmw== Message-ID: <729bbf75faad7c3a4ed74fffc3d84007.sboyd@kernel.org> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20231122-x1e80100-clk-tcsrcc-v1-2-43078c6d6452@linaro.org> References: <20231122-x1e80100-clk-tcsrcc-v1-0-43078c6d6452@linaro.org> <20231122-x1e80100-clk-tcsrcc-v1-2-43078c6d6452@linaro.org> Subject: Re: [PATCH 2/2] clk: qcom: Add TCSR clock driver for x1e80100 From: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa To: Abel Vesa , Andy Gross , Bjorn Andersson , Conor Dooley , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Rajendra Nayak , Rob Herring Date: Mon, 27 Nov 2023 15:41:24 -0800 User-Agent: alot/0.10 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Abel Vesa (2023-11-22 05:42:13) > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index ad1acd9b7426..6ed9c89d9070 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -1116,4 +1116,12 @@ config SM_VIDEOCC_8450 > SM8450 devices. > Say Y if you want to support video devices and functionality su= ch as > video encode/decode. > + > +config X1E_TCSRCC_80100 Is the config symbol intentionally namespaced for X1E prefix to group one SoC? Why not X1E80100_TCSRCC then? > + tristate "X1E80100 TCSR Clock Controller" > + depends on ARM64 || COMPILE_TEST > + select QCOM_GDSC > + help > + Support for the TCSR clock controller on X1E80100 devices. > + Say Y if you want to use peripheral devices such as SD/UFS. > endif > diff --git a/drivers/clk/qcom/tcsrcc-x1e80100.c b/drivers/clk/qcom/tcsrcc= -x1e80100.c > new file mode 100644 > index 000000000000..2ec142c3d1f9 > --- /dev/null > +++ b/drivers/clk/qcom/tcsrcc-x1e80100.c > @@ -0,0 +1,295 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reser= ved. > + * Copyright (c) 2023, Linaro Limited > + */ > + > +#include > +#include > +#include > +#include > + > +#include > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-pll.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "clk-regmap-divider.h" > +#include "clk-regmap-mux.h" > +#include "common.h" > +#include "reset.h" > + > +enum { > + DT_BI_TCXO_PAD, > +}; > + > +static struct clk_branch tcsr_edp_clkref_en =3D { > + .halt_reg =3D 0x15130, > + .halt_check =3D BRANCH_HALT_DELAY, > + .clkr =3D { > + .enable_reg =3D 0x15130, > + .enable_mask =3D BIT(0), > + .hw.init =3D &(const struct clk_init_data) { > + .name =3D "tcsr_edp_clkref_en", > + .ops =3D &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch tcsr_pcie_2l_4_clkref_en =3D { > + .halt_reg =3D 0x15100, > + .halt_check =3D BRANCH_HALT_DELAY, Why are these all branch halt delay but still have a halt_reg? > + .clkr =3D { > + .enable_reg =3D 0x15100, > + .enable_mask =3D BIT(0), > + .hw.init =3D &(struct clk_init_data){ const? > + .name =3D "tcsr_pcie_2l_4_clkref_en", > + .parent_data =3D &(const struct clk_parent_data){ > + .index =3D DT_BI_TCXO_PAD, > + },