From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52B855B211 for ; Mon, 27 Jan 2025 14:34:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737988462; cv=none; b=hyBDAm1br18uEPgV7gh0fvu9YjcIn6+H+wOxWPEjhCERSdGiUYvTYEZT7iNiitNV7P0GjzfdRrbMkj8lhKLApp/R3LYPJgjM2Fsit3a3X1gaIPpUNfaGaR/ofVBzK/67WzKeUOKZ4zKg7wqTGrCaT4b+pF3r14O4HjiCYf/hHtg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737988462; c=relaxed/simple; bh=cQMm3QlLbULCsHd2OGVtYmYNrx+R1yyQyMurtE+ZM34=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=T9b2GXeHVOGoR1FvBwlqAx+5mrXZYvkPs6Mnv8NW0qgDLbuwsPrC8ky5yXbMQwqU6/fc4HOvF7/jOAUqTRcTfk0vjdK4E9QXsPV1ZtCYhwDvkWZeEj2doXzGRbKoBNkPhGph0PTTGrxgY1rCKY7GoPeUSAAIbgskNXgP+5kOMYQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AWLgCG8U; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AWLgCG8U" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737988461; x=1769524461; h=message-id:date:mime-version:subject:to:references:from: in-reply-to:content-transfer-encoding; bh=cQMm3QlLbULCsHd2OGVtYmYNrx+R1yyQyMurtE+ZM34=; b=AWLgCG8UOKD8QVJ7XCF7J2HW5kW1vqD0/+Ee0qLy7FucdAdRXa3oDN7P j7ns2+cYd33b75XZQjpc91nDC0W9FMFoSFksDrG6gIRcs/XKf57c9036s eMZlOXgjWfmgq6VwvKlfCAHMdTu0I3qIEeQ25WQ19IRvq8vHwpVNeomza +rZ/I0uasjvZCm80KCdpNrp09ZsExTr6IBT7gRvVC6iTNqWpJ0t0eK+u+ 0qVkU+8zsAV7SPSdVCdK3ReGcJuxus0Vp/sHgtjHyEqb8vclpZwucqN12 YGl8bILTK/J7ibT2nzUteBC38msQbSWgZqXXjCYgH1ilXaLF2tHJbmDTy w==; X-CSE-ConnectionGUID: mc/f2ROXRAuYttKG2gbypQ== X-CSE-MsgGUID: qAM/+aRxTZCE+SFJawE1/g== X-IronPort-AV: E=McAfee;i="6700,10204,11328"; a="38337786" X-IronPort-AV: E=Sophos;i="6.13,238,1732608000"; d="scan'208";a="38337786" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2025 06:34:21 -0800 X-CSE-ConnectionGUID: 7QbDLHcmQk2wmhyPUJyGfg== X-CSE-MsgGUID: E1rz6E2DQXOXUQzVi0CWwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="139304226" Received: from linux.intel.com ([10.54.29.200]) by fmviesa001.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2025 06:34:20 -0800 Received: from [10.246.136.10] (kliang2-mobl1.ccr.corp.intel.com [10.246.136.10]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by linux.intel.com (Postfix) with ESMTPS id 7F36320B5713; Mon, 27 Jan 2025 06:34:19 -0800 (PST) Message-ID: <72dacfd6-4102-4efb-a699-875fa17acb28@linux.intel.com> Date: Mon, 27 Jan 2025 09:34:18 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] perf/x86/intel: Clean up PEBS-via-PT on hybrid To: Adrian Hunter , peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org References: <20250124183432.3565061-1-kan.liang@linux.intel.com> <61c1018e-fcdc-461b-8de4-845b33f619c0@intel.com> Content-Language: en-US From: "Liang, Kan" In-Reply-To: <61c1018e-fcdc-461b-8de4-845b33f619c0@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2025-01-27 3:19 a.m., Adrian Hunter wrote: > On 24/01/25 20:34, kan.liang@linux.intel.com wrote: >> From: Kan Liang >> >> The PEBS-via-PT feature is exposed for the e-core of some hybrid >> platforms, e.g., ADL and MTL. But it never works. >> >> $ dmesg | grep PEBS >> [ 1.793888] core: cpu_atom PMU driver: PEBS-via-PT >> >> $ perf record -c 1000 -e '{intel_pt/branch=0/, >> cpu_atom/cpu-cycles,aux-output/pp}' -C8 >> Error: >> The sys_perf_event_open() syscall returned with 22 (Invalid argument) >> for event (cpu_atom/cpu-cycles,aux-output/pp). >> "dmesg | grep -i perf" may provide additional information. >> >> The "PEBS-via-PT" is printed if the corresponding bit of per-PMU >> capabilities is set. Since the feature is supported by the e-core HW, >> perf sets the bit for e-core. However, for Intel PT, if a feature is not >> supported on all CPUs, it is not supported at all. The PEBS-via-PT event >> cannot be created successfully. >> >> The PEBS-via-PT is no longer enumerated on the latest hybrid platform. It >> will be deprecated on future platforms with Arch PEBS. Let's remove it >> from the existing hybrid platforms. >> >> Fixes: d9977c43bff8 ("perf/x86: Register hybrid PMUs") >> Signed-off-by: Kan Liang >> Cc: Adrian Hunter >> Cc: Alexander Shishkin >> --- >> arch/x86/events/intel/core.c | 10 ---------- >> arch/x86/events/intel/ds.c | 2 +- >> 2 files changed, 1 insertion(+), 11 deletions(-) >> >> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c >> index 7f1b6b90a5fb..0a1030eb6db8 100644 >> --- a/arch/x86/events/intel/core.c >> +++ b/arch/x86/events/intel/core.c >> @@ -4981,11 +4981,6 @@ static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) >> else >> pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); >> >> - if (pmu->intel_cap.pebs_output_pt_available) >> - pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; >> - else >> - pmu->pmu.capabilities &= ~PERF_PMU_CAP_AUX_OUTPUT; >> - >> intel_pmu_check_event_constraints(pmu->event_constraints, >> pmu->cntr_mask64, >> pmu->fixed_cntr_mask64, >> @@ -5063,9 +5058,6 @@ static bool init_hybrid_pmu(int cpu) >> >> pr_info("%s PMU driver: ", pmu->name); >> >> - if (pmu->intel_cap.pebs_output_pt_available) >> - pr_cont("PEBS-via-PT "); >> - >> pr_cont("\n"); >> >> x86_pmu_show_pmu_cap(&pmu->pmu); >> @@ -6420,11 +6412,9 @@ static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) >> pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; >> if (pmu->pmu_type & hybrid_small_tiny) { >> pmu->intel_cap.perf_metrics = 0; >> - pmu->intel_cap.pebs_output_pt_available = 1; >> pmu->mid_ack = true; >> } else if (pmu->pmu_type & hybrid_big) { >> pmu->intel_cap.perf_metrics = 1; >> - pmu->intel_cap.pebs_output_pt_available = 0; >> pmu->late_ack = true; >> } >> } >> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c >> index 13a78a8a2780..123b0e4392b4 100644 >> --- a/arch/x86/events/intel/ds.c >> +++ b/arch/x86/events/intel/ds.c >> @@ -2742,7 +2742,7 @@ void __init intel_ds_init(void) >> } >> pr_cont("PEBS fmt%d%c%s, ", format, pebs_type, pebs_qual); >> >> - if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) { >> + if (x86_pmu.intel_cap.pebs_output_pt_available) { > > I'd suggest keeping the !is_hybrid() check here > since it documents and enforces the effective policy. Sigh, the !is_hybrid() should never work here either. Because the intel_ds_init() is invoked before intel_pmu_init_hybrid(), which enable perf_is_hybrid. I think we'd better remove it, but I will add some comments to explain the status of PEBS-via-PT on hybrid instead. For example, /* * The PEBS-via-PT is not supported on hybrid platforms, because not all * CPUs of a hybrid machine support the feature. The global * x86_pmu.intel_cap, which only contains the common capabilities, is * used to check the availability of the feature. The per-PMU * pebs_output_pt_available in a hybrid machine will be ignored. */ Thanks, Kan > >> pr_cont("PEBS-via-PT, "); >> x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT; >> } > >