From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D221290092; Wed, 9 Jul 2025 14:11:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752070318; cv=none; b=dtsMqOLb8oCjfpo6cTTzHG4SEEBYjBZ4A6BzYQPhv5y+G/cCgDhehzrE2wPiqh+E+OxOie5psJneNDhKn/wQf3vslxPSsFPvrv6w70lKOpe9DGSfcOyEGc61aMtEYtuQQKIN0UmXwes8SNpC+U1P9cmtPlOO7iqWkac0B6KkY7s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752070318; c=relaxed/simple; bh=MP8y7OgpetDh3M79PleMX8TjA4AwgjOhJ4DgQjJGgRM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=utehtC1o9QLpb9I4B8if5lTjy2hBiy0JjeYA0DEd+/uR82DjQA00ndrKwEkicuQFo8GcF8uvE9NqGzYIrjzR1fu8/I9irR0nxUnxFjN7xkGeqQpcXuKxWuryhMndXaAeUTSj8kGDOjNNqWNz7426nZEYcaARHXVwlLiZey7/XEs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tua7tl5C; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tua7tl5C" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BE546C4CEEF; Wed, 9 Jul 2025 14:11:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752070317; bh=MP8y7OgpetDh3M79PleMX8TjA4AwgjOhJ4DgQjJGgRM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=tua7tl5CR2shKodoU+r6z3cIdXQWuEXLopgPRh9M7/cSvu8WZsSysvpY3RIWew0hZ BhkS02BGy3Xm5tojLWZB0fTzLFtPtw0fgkNtAbNbzX4FMF5Y16IKAbD217aXUSeLq8 4roJ/cR+jQqWrcx4JcSg9mpL4+A/grmBIpmXjnGAntcgloJROFXXMnq04hVJeG4jIf 7T26wA6gI0HXvt5snzYdiL8dZuBs+61LtxRkFIA6Ln3tOLC82njLLnIrWa/6CfHjIX d1QnjLe0C+Mt59ze3U45rzdTNh1VMIeDKVZF2r7h6EDrNToReb9p+gN3lNGC9O9qEj kKyFB5JK0PI+w== Message-ID: <7311e4b6-8832-46fc-94b8-4ebcb2592926@kernel.org> Date: Wed, 9 Jul 2025 16:11:52 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/9] dt-bindings: gpio: add bindings for the QIXIS FPGA based GPIO controller To: Ioana Ciornei Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Shawn Guo , Michael Walle , Lee Jones , Frank Li References: <20250709112658.1987608-1-ioana.ciornei@nxp.com> <20250709112658.1987608-2-ioana.ciornei@nxp.com> <9aff4894-a8aa-47d2-8800-62959e064254@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 09/07/2025 15:55, Ioana Ciornei wrote: > On Wed, Jul 09, 2025 at 02:14:47PM +0200, Krzysztof Kozlowski wrote: >> On 09/07/2025 13:26, Ioana Ciornei wrote: >>> Add a device tree binding for the QIXIS FPGA based GPIO controller. >>> Depending on the board, the QIXIS FPGA exposes registers which act as a >>> GPIO controller, each with 8 GPIO lines of fixed direction. >>> >>> Since each QIXIS FPGA layout has its particularities, add a separate >>> compatible string for each board/GPIO register combination supported. >>> >>> Signed-off-by: Ioana Ciornei >> >> Your changelog explains patches, which is kind of redundant - we see >> that - but does not explain the dependency you have here between patches. >> > > Do you mean the logical dependency between all the components like > FPGAs, GPIOs etc? I can expand on that, sure. I will also update the > cover letter with some of the information below. > If this is not what you are looking for, please let me know. I meant here cover letter, not changelog. It does not explain dependencies between patches. You just explain what each patch is doing - this is completely redundant cover letter. > > Layerscape boards such as those that I update here have a QIXIS FPGA > accessible through I2C. This FPGA exposes a set of registers which can > be used to monitor the status of different components, configure muxing, > act as GPIO controllers etc. > > Since the register layout that this device exposes is different on a per > board basis, each board has a different compatible string such as the > one that patch 2/9 adds - fsl,lx2160ardb-fpga. > > Going deeper, some of these registers are acting as GPIO controllers > exposing status/control of different SFP cages on the board. For these > kind of registers the new gpio-regmap driver is added. > >> A nit, subject: drop second/last, redundant "bindings". The >> "dt-bindings" prefix is already stating that these are bindings. >> See also: >> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 >> > > Sure. Will fix. > >>> --- >>> .../bindings/gpio/fsl,fpga-gpio.yaml | 44 +++++++++++++++++++ >>> 1 file changed, 44 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/gpio/fsl,fpga-gpio.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/gpio/fsl,fpga-gpio.yaml b/Documentation/devicetree/bindings/gpio/fsl,fpga-gpio.yaml >>> new file mode 100644 >>> index 000000000000..dc7b6c0d9b40 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/gpio/fsl,fpga-gpio.yaml >>> @@ -0,0 +1,44 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/gpio/fsl,fpga-gpio.yaml >>> +$schema: http://devicetree.org/meta-schemas/core.yaml >>> + >>> +title: GPIO controller embedded in the NXP QIXIS FPGA >>> + >>> +maintainers: >>> + - Ioana Ciornei >>> + >>> +description: | >>> + This module is part of the QIXIS FPGA found on some Layerscape boards such as >>> + LX2160ARDB and LS1046AQDS. For more details see >>> + ../board/fsl,fpga-qixis-i2c.yaml. >> >> There are no "board" bindings, so this does not feel like correct path. > > As you have seen already in patch 2/9 there is already a dt-binding in > the board/ folder. > >> >>> + >>> + Each controller supports a maximum of 8 GPIO lines and each line has a fixed >>> + direction which cannot be changed using a direction register. >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - fsl,lx2160ardb-fpga-gpio-sfp2 >>> + - fsl,lx2160ardb-fpga-gpio-sfp3 >> >> What is the difference between these? > > The layout of the registers backing these two GPIO controllers is the > same but they each expose status/control of different SFP cages. So same devices? Why do they need separate compatibles? Best regards, Krzysztof