* [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents
@ 2022-10-13 15:13 David Virag
2022-10-13 14:35 ` Krzysztof Kozlowski
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: David Virag @ 2022-10-13 15:13 UTC (permalink / raw)
Cc: David Virag, Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd,
linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel
"div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
2 to achieve a by 4 division, thus their parents are the respective
"div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
This leads to the kernel thinking "div4"s and everything under them run
at 2x the clock speed. Fix this.
Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
Signed-off-by: David Virag <virag.david003@gmail.com>
---
drivers/clk/samsung/clk-exynos7885.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
index a7b106302706..368c50badd15 100644
--- a/drivers/clk/samsung/clk-exynos7885.c
+++ b/drivers/clk/samsung/clk-exynos7885.c
@@ -182,7 +182,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
- DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
+ DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
@@ -190,7 +190,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
- DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
+ DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
/* CORE */
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents
2022-10-13 15:13 [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents David Virag
@ 2022-10-13 14:35 ` Krzysztof Kozlowski
2022-10-13 19:36 ` Chanwoo Choi
2022-10-18 13:19 ` Krzysztof Kozlowski
2 siblings, 0 replies; 4+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-13 14:35 UTC (permalink / raw)
To: David Virag
Cc: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar,
Michael Turquette, Stephen Boyd, linux-samsung-soc, linux-clk,
linux-arm-kernel, linux-kernel
On 13/10/2022 11:13, David Virag wrote:
> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
> 2 to achieve a by 4 division, thus their parents are the respective
> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
> This leads to the kernel thinking "div4"s and everything under them run
> at 2x the clock speed. Fix this.
>
> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
> Signed-off-by: David Virag <virag.david003@gmail.com>
> ---
Looks good, I'll take it after merge window.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents
2022-10-13 15:13 [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents David Virag
2022-10-13 14:35 ` Krzysztof Kozlowski
@ 2022-10-13 19:36 ` Chanwoo Choi
2022-10-18 13:19 ` Krzysztof Kozlowski
2 siblings, 0 replies; 4+ messages in thread
From: Chanwoo Choi @ 2022-10-13 19:36 UTC (permalink / raw)
To: David Virag
Cc: Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd,
linux-samsung-soc, linux-clk, linux-arm-kernel, linux-kernel
On 22. 10. 14. 00:13, David Virag wrote:
> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
> 2 to achieve a by 4 division, thus their parents are the respective
> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
> This leads to the kernel thinking "div4"s and everything under them run
> at 2x the clock speed. Fix this.
>
> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
> Signed-off-by: David Virag <virag.david003@gmail.com>
> ---
> drivers/clk/samsung/clk-exynos7885.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
> index a7b106302706..368c50badd15 100644
> --- a/drivers/clk/samsung/clk-exynos7885.c
> +++ b/drivers/clk/samsung/clk-exynos7885.c
> @@ -182,7 +182,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
> CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> - DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
> + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
> CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
> CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
> @@ -190,7 +190,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
> CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> - DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
> + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
> CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
>
> /* CORE */
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Thanks for fix-up.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents
2022-10-13 15:13 [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents David Virag
2022-10-13 14:35 ` Krzysztof Kozlowski
2022-10-13 19:36 ` Chanwoo Choi
@ 2022-10-18 13:19 ` Krzysztof Kozlowski
2 siblings, 0 replies; 4+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-18 13:19 UTC (permalink / raw)
To: David Virag
Cc: Krzysztof Kozlowski, Stephen Boyd, linux-arm-kernel,
linux-samsung-soc, Tomasz Figa, linux-kernel, Chanwoo Choi,
Sylwester Nawrocki, linux-clk, Michael Turquette, Alim Akhtar
On Thu, 13 Oct 2022 17:13:40 +0200, David Virag wrote:
> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
> 2 to achieve a by 4 division, thus their parents are the respective
> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
> This leads to the kernel thinking "div4"s and everything under them run
> at 2x the clock speed. Fix this.
>
>
> [...]
Applied, thanks!
[1/1] clk: samsung: exynos7885: Correct "div4" clock parents
https://git.kernel.org/krzk/linux/c/ef80c95c29dc67c3034f32d93c41e2ede398e387
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-10-13 15:13 [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents David Virag
2022-10-13 14:35 ` Krzysztof Kozlowski
2022-10-13 19:36 ` Chanwoo Choi
2022-10-18 13:19 ` Krzysztof Kozlowski
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