Re: [PATCH v1] eSPI: add Aspeed AST2500 eSPI driver to boot a host with PCH runs on eSPI

["Wang, Haiyue" <haiyue.wang@linux.intel.com>]

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Hi Arnd,

Thanks for your reply. Happy new year! :-)

On 2017-12-31 07:10, Arnd Bergmann wrote:
> On Fri, Dec 29, 2017 at 2:53 AM, Haiyue Wang
> <haiyue.wang@linux.intel.com> wrote:
>> When PCH works under eSPI mode, the PMC (Power Management Controller) in
>> PCH is waiting for SUS_ACK from BMC after it alerts SUS_WARN. It is in
>> dead loop if no SUS_ACK assert. This is the basic requirement for the BMC
>> works as eSPI slave.
>>
>> Also for the host power on / off actions, from BMC side, the following VW
>> (Virtual Wire) messages are done in firmware:
>> 1. SLAVE_BOOT_LOAD_DONE / SLAVE_BOOT_LOAD_STATUS
>> 2. SUS_ACK
>> 3. OOB_RESET_ACK
>> 4. HOST_RESET_ACK
> I have not looked at the driver contents yet, but I'm adding the SPI
> maintainer and
> mailing list to Cc here for further discussion. Can you clarify how
> the eSPI slave
> mode relates to SPI slaves that we already support? I was under the impression
> that the difference between SPI and eSPI is mainly on the master side, but that
> any SPI slave can also act as an eSPI slave. Would this driver fit into the SPI
> slave framework, possibly with some extensions to the generic abstraction?
In simple word, the eSPI uses the SPI interface pin definition, but it 
will replace Low Pin Count (LPC)
interface. From its name, sure, it will confuse you! ;-)
> It also seems rather inflexible to have a single driver that is responsible both
> for the transport (eSPI register level interface for ASPEED) and the high-level
> protocol (talking to an Intel PCH), since either half of the work could be
> done elsewhere, using either a different eSPI slave implementation, or
> a different
> host architecture)
Yes, eSPI has the architecture such as transaction layer, link Layer; 
all of it is about the **silicon**
design. That's why I put the driver under /misc directory, not /spi 
directory.

>         Arnd

---
BR,

Haiyue

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