Re: [PATCH] drivers/block/xsysace - replace in(out)_8/in(out)_be16/in(out)_le16 with generic iowrite(read)8/16(be)

[Arnd Bergmann <arnd@arndb.de>]

On Tuesday 05 February 2013 18:03:31 Alexey Brodkin wrote:
> The Xilinx System ACE Compact Flash chip is a true little-endian device 
> and the PLB is a big-endian bus. Therefore the XPS System ACE Interface 
> Controller will do a bit-swap in each byte when connecting the PLB data 
> bus to the System ACE data bus as shown in Table 2.
> 
> Note however, that the XPS System ACE Interface Controller does not 
> perform the byte swapping necessary to interface to a little-endian 
> device when configured to use 16-bit mode. Therefore, the software 
> drivers provided for this core will perform the necessary byte-swapping 
> to correctly interface to the Xilinx System ACE Compact Flash chip as 
> shown in Table 3.

Ok. In this case, I would recommend making the default for this driver
little-endian, and adding a quirk for broken hardware bridges like the
one you cited to have a mixed-endian mode if configured so at compile
time.

It seems that on all normal platforms, this device should behave as
little-endian, while the Xilinx bridge can be either big-endian
or little-endian, depending on whether it is used in 8-bit or 16-bit
mode, so if we are using this, it cannot be known at compile time.

	Arnd