From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48A63231A21; Sat, 18 Oct 2025 15:39:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760801989; cv=none; b=ltBkZAGs0Wk4bcowvfzcUzWTzf43Rk72b9B7uQZLfG1o4iqxezf67m7/9Ou13RYAmgdHWSYezhqVXG6nq9c7ewHQOzhcAr4xthtwBUFCUZpIpnWZWZOfBDMLrwb825EXPIBBeCe8qYGqESzeOniAMttCZBbipPECOmFlIfcz8mk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760801989; c=relaxed/simple; bh=uPs/OpEf+XULCClITk1PlNX/3UzNgoknxybf2RIh+N0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=te/BzqcMWZRzSL1tLgX3iVqOuviviufBFgaTeUb3EhCJqV89OENPaU3xO7JdHxF77kn+tOMdv6e+uX4wlLQ6uuuCmcvCp8duBSiuJB0Rn6BJ3a4Q/mSGLZVQaQ4ygQBmXcVXGreGsC5iGw3XiIgYwU1tvkA3Dta7eEHSgHoX2iQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p885U9Jy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p885U9Jy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 781D4C116B1; Sat, 18 Oct 2025 15:39:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760801988; bh=uPs/OpEf+XULCClITk1PlNX/3UzNgoknxybf2RIh+N0=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=p885U9JyuAkB8hB1yBq/H3SQ5c888kfz+QnPugX0oDzFBWUQFEK3wqCQN+abJ28LX d3Pyolqqjvd00QvVHsfEtGvgAmO6qPMgRHvdE8ObjybIA0pWcy56vS+Qi3Cq+CLVXB jWFs/owiDqnbJoONpNo8AZCCWehWY5evFdE02s/eY2dbxNm4ZuVKPYIANcMzhNogfB B1kmNbO1vly2AI2TidbMsyiglMxI9YPfW2j10we5utTH8/094UqzrkffKTIwpm1vyI 7hqooVSBOJ4dUuVHs4r7km87Q1/NCoIwxbqzHOckzUML9qz3YVRk7NjSkdeLcDV6hW 5KnyxGZaxm4fg== Message-ID: <78445973-6a5e-4dd8-a661-4e784af49b4e@kernel.org> Date: Sat, 18 Oct 2025 17:39:43 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 02/10] dt-bindings: phy: qcom,qmp-usb: Add Glymur USB UNI PHY compatible To: Wesley Cheng , krzk+dt@kernel.org, conor+dt@kernel.org, konrad.dybcio@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, kishon@kernel.org, vkoul@kernel.org, gregkh@linuxfoundation.org, robh@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251006222002.2182777-1-wesley.cheng@oss.qualcomm.com> <20251006222002.2182777-3-wesley.cheng@oss.qualcomm.com> <00408896-2e25-2dd1-6e6e-2195317ee7fb@oss.qualcomm.com> <14bc2a85-0f1d-3834-9b9c-32654348603a@oss.qualcomm.com> <387c707e-613d-433b-a76d-16ef10dabc59@kernel.org> <2a70f878-269c-1b40-2e8c-77b5851de9a1@oss.qualcomm.com> <99ab26d3-eb44-401d-8a7c-1d9efd2a1a10@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 18/10/2025 02:20, Wesley Cheng wrote: > > > On 10/16/2025 9:41 PM, Krzysztof Kozlowski wrote: >> On 17/10/2025 02:15, Wesley Cheng wrote: >>>>> Technically its all handling the same clock branch (CXO), we have the >>>>> TCSR clkref register that allows us to gate the CXO to the USB PHY, as >>>> >>>> >>>> Ah, exactly. Then clkref is not a clock. You need rather proper clock >>>> hierarchy. >>>> >>>>> CXO is shared across several HW blocks, so it allows us to properly >>>>> powerdown the PHY even though other clients are voting for CXO on. Then >>>>> we obviously have to remove our vote to the overall CXO, so that it can >>>>> potentially be shutdown. >>>>> >>>>> Maybe we can rename it to "clkref" for the CXO handle and >>>>> "clkref_switch" for the TCSRCC handle? >>>> >>>> Naming is better, but it is still not correct. This is not independent >>>> clock signal. It is the same clock. >>>> >>> >>> Hmmm... I guess that's why I kept the same clkref tag, to denote that >>> its the same clock, but one is a switch/gate for it. Would you happen >>> to have any suggestions you might have that makes it clearer for >>> everyone to understand? >> To me it looks like: >> >> |-----| |-----------| |------------------| >> |clock|------------|TCSRCC gate|-----------|clkref to this dev| >> |-----| |-----------| |------------------| >> >> So you need proper clock controller for TCSR (TCSR Clock Controller, in >> short TCSRCC, what a surprise!) which will take input, add gate and >> produce clock for this device. >> >> Nothing non-standard, all Qualcomm SoCs have it, every other platform >> has it in some way. >> > > Hi Krzystof, > > Yes, the design is exactly how you outlined it above. How about clkref Hm? There is no connection between the clock and the device. Do you see any line going there? > for the clock and tcsrcc_switch for the clkref switch? That removes any > notation that the gate/switch is an actual clock... You really did not get the point of this entire discussion. Best regards, Krzysztof