[PATCH 8/8] arm64: tegra: Update AHUB clock parent and rate

Sameer Pujar
2023-06-22T11:36:30Z

I2S data sanity test failures are seen at lower AHUB clock rates
on Tegra234. The Tegra194 uses the same clock relationship for AHUB
and it is likely that similar issues would be seen. Thus update the
AHUB clock parent and rates here as well for Tegra194, Tegra186
and Tegra210.

Fixes: 177208f7b06d ("arm64: tegra: Add DT binding for AHUB components")
Cc: stable@vger.kernel.org
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 3 ++-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 3 ++-
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 7e4c496f..2b3bb5d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -135,7 +135,8 @@
clocks = <&bpmp TEGRA186_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
- assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
+ assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
+ assigned-clock-rates = <81600000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x02900800 0x02900800 0x11800>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 154fc8c..33f92b7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -231,7 +231,8 @@
clocks = <&bpmp TEGRA194_CLK_AHUB>;
clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
- assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
+ assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
+ assigned-clock-rates = <81600000>;
status = "disabled";

#address-cells = <2>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 617583f..e7b4e30 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1386,7 +1386,8 @@
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "ahub";
assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
- assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
+ assigned-clock-rates = <81600000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702d0000 0x702d0000 0x0000e400>;
--
2.7.4