[PATCH v7 0/2] Add notifier for PLL0 clock and set it 1.5GHz on the JH7110 SoC

[PATCH v7 0/2] Add notifier for PLL0 clock and set it 1.5GHz on the JH7110 SoC

[Xingyu Wu]

This patch is to add the notifier for PLL0 clock and set the PLL0 rate
to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.

The first patch is to add the notifier for PLL0 clock. Setting the PLL0
rate need the son clock (cpu_root) to switch its parent clock to OSC 
clock and switch it back after setting PLL0 rate. It need to use the 
cpu_root clock from SYSCRG and register the notifier in the SYSCRG
driver.

The second patch is to set cpu_core rate to 500MHz and PLL0 rate to
1.5GHz to fix the problem about the lower rate of CPUfreq on the 
visionfive board. The cpu_core clock rate is set to 500MHz first to
ensure that the cpu frequency will not suddenly become high and the cpu 
voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz.
The cpu voltage and frequency are then adjusted together by CPUfreq.

According to some tests, U-Boot can also run 1.5G so that the DTS from
kernel can be used on the U-Boot and could not cause any problems. So
the way of patch v5 works.

Changes since v6:
- Used the patch 1 from v5 and added the reviewed tag.
- Modified the patch 2 from v5 to fit the new jh7110-common.dtsi.

v6: https://lore.kernel.org/all/20240603020607.25122-1-xingyu.wu@starfivetech.com/

Changes since v5:
- Set the rate to 1.5G in the driver instead of DTS.

v5: https://lore.kernel.org/all/20240507065319.274976-1-xingyu.wu@starfivetech.com/

Changes since v4: 
- Fixed the wrong words.
- Added the Fixes tag in first patch.

v4: https://lore.kernel.org/all/20240410033148.213991-1-xingyu.wu@starfivetech.com/

Changes since v3: 
- Added the notifier for PLL0 clock.
- Set cpu_core rate in DTS 

v3: https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivetech.com/

Changes since v2: 
- Made the steps into the process into the process of setting PLL0 rate

v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/

Changes since v1: 
- Added the fixes tag in the commit.

v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/

Xingyu Wu (2):
  clk: starfive: jh7110-sys: Add notifier for PLL0 clock
  riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by
    setting PLL0 rate to 1.5GHz

 .../boot/dts/starfive/jh7110-common.dtsi      |  6 ++++
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++++++++++++++++-
 drivers/clk/starfive/clk-starfive-jh71x0.h    |  2 ++
 3 files changed, 38 insertions(+), 1 deletion(-)

-- 
2.34.1

[PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock

[Xingyu Wu]

Add notifier function for PLL0 clock. In the function, the cpu_root clock
should be operated by saving its current parent and setting a new safe
parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
rate, it should be switched back to the original parent clock.

Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++++++++++++++++-
 drivers/clk/starfive/clk-starfive-jh71x0.h    |  2 ++
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 8f5e5abfa178..dafa3ae71751 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
 }
 EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
 
+/*
+ * This clock notifier is called when the rate of PLL0 clock is to be changed.
+ * The cpu_root clock should save the curent parent clock and swicth its parent
+ * clock to osc before PLL0 rate will be changed. Then swicth its parent clock
+ * back after the PLL0 rate is completed.
+ */
+static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb,
+				       unsigned long action, void *data)
+{
+	struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb);
+	struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
+	int ret = 0;
+
+	if (action == PRE_RATE_CHANGE) {
+		struct clk *osc = clk_get(priv->dev, "osc");
+
+		priv->original_clk = clk_get_parent(cpu_root);
+		ret = clk_set_parent(cpu_root, osc);
+		clk_put(osc);
+	} else if (action == POST_RATE_CHANGE) {
+		ret = clk_set_parent(cpu_root, priv->original_clk);
+	}
+
+	return notifier_from_errno(ret);
+}
+
 static int __init jh7110_syscrg_probe(struct platform_device *pdev)
 {
 	struct jh71x0_clk_priv *priv;
@@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
 		if (IS_ERR(priv->pll[0]))
 			return PTR_ERR(priv->pll[0]);
 	} else {
-		clk_put(pllclk);
+		priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
+		ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
+		if (ret)
+			return ret;
 		priv->pll[0] = NULL;
 	}
 
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
index 23e052fc1549..e3f441393e48 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
@@ -114,6 +114,8 @@ struct jh71x0_clk_priv {
 	spinlock_t rmw_lock;
 	struct device *dev;
 	void __iomem *base;
+	struct clk *original_clk;
+	struct notifier_block pll_clk_nb;
 	struct clk_hw *pll[3];
 	struct jh71x0_clk reg[];
 };
-- 
2.34.1

[PATCH v7 2/2] riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz

[Xingyu Wu]

CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
250/333/500/1000MHz in fact.

The PLL0 rate should be default set to 1.5GHz and set the
cpu_core rate to 500MHz in safe.

Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index ca2d44d59d48..c7771b3b6475 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -365,6 +365,12 @@ spi_dev0: spi@0 {
 	};
 };
 
+&syscrg {
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
+			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
+	assigned-clock-rates = <500000000>, <1500000000>;
+};
+
 &sysgpio {
 	i2c0_pins: i2c0-0 {
 		i2c-pins {
-- 
2.34.1

RE: [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock

[Hal Feng]

> On 26.08.24 16:04, Xingyu Wu wrote:
> Add notifier function for PLL0 clock. In the function, the cpu_root clock should
> be operated by saving its current parent and setting a new safe parent (osc
> clock) before setting the PLL0 clock rate. After setting PLL0 rate, it should be
> switched back to the original parent clock.
> 
> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

Reviewed-by: Hal Feng <hal.feng@starfivetech.com>

RE: [PATCH v7 2/2] riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz

[Hal Feng]

> On 26.08.24 16:05, Xingyu Wu wrote:
> CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
> But now PLL0 rate is 1GHz and the cpu frequency loads become
> 250/333/500/1000MHz in fact.
> 
> The PLL0 rate should be default set to 1.5GHz and set the cpu_core rate to
> 500MHz in safe.
> 
> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

Reviewed-by: Hal Feng <hal.feng@starfivetech.com>

Re: [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock

[Stephen Boyd]

Quoting Xingyu Wu (2024-08-26 01:04:29)
> Add notifier function for PLL0 clock. In the function, the cpu_root clock
> should be operated by saving its current parent and setting a new safe
> parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
> rate, it should be switched back to the original parent clock.
> 
> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---

What is the urgency of this patch? I can't tell from the commit text, so
I'm assuming it can bake in clk-next for a few weeks.

RE: [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock

[Xingyu Wu]

On 29/08/2024 04:19, Stephen Boyd wrote:
> 
> Quoting Xingyu Wu (2024-08-26 01:04:29)
> > Add notifier function for PLL0 clock. In the function, the cpu_root
> > clock should be operated by saving its current parent and setting a
> > new safe parent (osc clock) before setting the PLL0 clock rate. After
> > setting PLL0 rate, it should be switched back to the original parent clock.
> >
> > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110
> > SoC")
> > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> > ---
> 
> What is the urgency of this patch? I can't tell from the commit text, so I'm
> assuming it can bake in clk-next for a few weeks.

Hi Stephen,

This is urgent. Without this patch, Cpufreq does not work and the CPU can't work in the best frequency of 1.5GHz. This patch can improve the performance of the visionfive-2 board.

Best regards,
Xingyu Wu

Re: [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock

[Michael Jeanson]

On 2024-08-26 04:04, Xingyu Wu wrote:
> Add notifier function for PLL0 clock. In the function, the cpu_root clock
> should be operated by saving its current parent and setting a new safe
> parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
> rate, it should be switched back to the original parent clock.
> 
> Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

Tested on a Visionfive2, on v6.11-rc5 the CPU is stuck at 1Ghz. With these 2
patches applied, CPU defaults to 1.5Ghz and can be set to 375 MHz, 500 MHz,
750 MHz.

Tested-By: Michael Jeanson <mjeanson@efficios.com>

RE: [PATCH v7 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock

[Stephen Boyd]

Quoting Xingyu Wu (2024-08-28 22:42:43)
> On 29/08/2024 04:19, Stephen Boyd wrote:
> > 
> > Quoting Xingyu Wu (2024-08-26 01:04:29)
> > > Add notifier function for PLL0 clock. In the function, the cpu_root
> > > clock should be operated by saving its current parent and setting a
> > > new safe parent (osc clock) before setting the PLL0 clock rate. After
> > > setting PLL0 rate, it should be switched back to the original parent clock.
> > >
> > > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110
> > > SoC")
> > > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> > > ---
> > 
> > What is the urgency of this patch? I can't tell from the commit text, so I'm
> > assuming it can bake in clk-next for a few weeks.
> 
> Hi Stephen,
> 
> This is urgent. Without this patch, Cpufreq does not work and the CPU can't work in the best frequency of 1.5GHz. This patch can improve the performance of the visionfive-2 board.
> 

Ok. I'll apply it to clk-fixes then.

Re: [PATCH v7 0/2] Add notifier for PLL0 clock and set it 1.5GHz on the JH7110 SoC

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

On Mon, 26 Aug 2024 16:04:28 +0800, Xingyu Wu wrote:
> This patch is to add the notifier for PLL0 clock and set the PLL0 rate
> to 1.5GHz to fix the lower rate of CPUfreq on the JH7110 SoC.
> 
> The first patch is to add the notifier for PLL0 clock. Setting the PLL0
> rate need the son clock (cpu_root) to switch its parent clock to OSC
> clock and switch it back after setting PLL0 rate. It need to use the
> cpu_root clock from SYSCRG and register the notifier in the SYSCRG
> driver.
> 
> [...]

Applied to riscv-soc-fixes, thanks!


[2/2] riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz
      https://git.kernel.org/conor/c/61f2e8a3a941

I applied this last night but forgot to send the ty email.