From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752466AbdH3Rbq (ORCPT ); Wed, 30 Aug 2017 13:31:46 -0400 Received: from mail.efficios.com ([167.114.142.141]:38780 "EHLO mail.efficios.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751435AbdH3Rbn (ORCPT ); Wed, 30 Aug 2017 13:31:43 -0400 Date: Wed, 30 Aug 2017 17:33:00 +0000 (UTC) From: Mathieu Desnoyers To: "Paul E. McKenney" Cc: Andy Lutomirski , Peter Zijlstra , linux-kernel , Boqun Feng , Andrew Hunter , maged michael , gromer , Avi Kivity , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Dave Watson , Andy Lutomirski , Will Deacon , Hans Boehm Message-ID: <794809000.30824.1504114380165.JavaMail.zimbra@efficios.com> In-Reply-To: <20170830144641.GV11320@linux.vnet.ibm.com> References: <20170827205035.25620-1-mathieu.desnoyers@efficios.com> <1463521395.16945.1503889546934.JavaMail.zimbra@efficios.com> <20170830144641.GV11320@linux.vnet.ibm.com> Subject: Re: [PATCH v2] membarrier: provide register sync core cmd MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Originating-IP: [167.114.142.141] X-Mailer: Zimbra 8.7.11_GA_1854 (ZimbraWebClient - FF52 (Linux)/8.7.11_GA_1854) Thread-Topic: membarrier: provide register sync core cmd Thread-Index: qXtVRq3dQoRYLSOx3UZv7Mmq5q518g== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ----- On Aug 30, 2017, at 10:46 AM, Paul E. McKenney paulmck@linux.vnet.ibm.com wrote: > On Tue, Aug 29, 2017 at 10:01:56PM -0700, Andy Lutomirski wrote: >> > On Aug 27, 2017, at 8:05 PM, Mathieu Desnoyers >> > wrote: >> > >> > ----- On Aug 27, 2017, at 3:53 PM, Andy Lutomirski luto@amacapital.net wrote: >> > >> >>> On Aug 27, 2017, at 1:50 PM, Mathieu Desnoyers >> >>> wrote: >> >>> >> >>> Add a new MEMBARRIER_CMD_REGISTER_SYNC_CORE command to the membarrier >> >>> system call. It allows processes to register their intent to have their >> >>> threads issue core serializing barriers in addition to memory barriers >> >>> whenever a membarrier command is performed. >> >>> >> >> >> >> Why is this stateful? That is, why not just have a new membarrier command to >> >> sync every thread's icache? >> > >> > If we'd do it on every CPU icache, it would be as trivial as you say. The >> > concern here is sending IPIs only to CPUs running threads that belong to the >> > same process, so we don't disturb unrelated processes. >> > >> > If we could just grab each CPU's runqueue lock, it would be fairly simple >> > to do. But we want to avoid hitting each runqueue with exclusive atomic >> > access associated with grabbing the lock. (cache-line bouncing) >> >> Hmm. Are there really arches where there is no clean implementation >> without this hacker? It seems rather unfortunate that munmap() can be >> done efficiently but this barrier can't be. >> >> At the very least, could there be a register command *and* a special >> sync command? I dislike the idea that the sync command does something >> different depending on some other state. Even better (IMO) would be a >> design where you ask for an isync and, if the arch can do it >> efficiently (x86), you get an efficient isync and, if the arch can't >> (arm64?) you take all the rq locks? > > In some cases I suspect that IPIs might be required. Regardless of > that, we might well need to provide a way for architectures to do > special things. > > But I must defer to Mathieu on this. Yes, I think you are both correct. It's better to expose a new command for code sync, so architectures have more freedom in how they choose to implement it. Thanks, Mathieu -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com