From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sg-3-11.ptr.tlmpb.com (sg-3-11.ptr.tlmpb.com [101.45.255.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13B5A225419 for ; Wed, 25 Jun 2025 07:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.45.255.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750836944; cv=none; b=SDUSxU+6ciBn7o2pRMRRWoqto/ahnScTFnNA09hdUc62VBEE9eqxfq8DLkd9n6y7eDdG5MlcWsutS8Sbxw9q8TrgF11qhYTcBQ7KM5QZmQo8RunA29N2FEvxNYToJV53EChGiPEc1yO3UyzikQNXa0Ah/40rKazKtUnwRxMBvdI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750836944; c=relaxed/simple; bh=a3DMDdHA6v6pJEswAP0XuoxOFgG+epMDo8MP/gCuqCc=; h=From:To:Cc:Mime-Version:Content-Type:Date:Message-Id:Subject: In-Reply-To:References; b=LBHBeU/XTR4c8AKajnYw/zRU/R3IGixfqPUJmanvYUwJbEADuSUMMQFJ5DSQlrrJm5RIzs0PtFeJyvvEwMRMkNgTLL/2+v35RFlQ9SxCIkjVrhWHGayNr7xW+1IZEZRm/3P5Nkpf/L9lNWYzmMVAHGJ8OeNtp+7uymVd8utpQhA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=lanxincomputing.com; spf=pass smtp.mailfrom=lanxincomputing.com; dkim=pass (2048-bit key) header.d=lanxincomputing-com.20200927.dkim.feishu.cn header.i=@lanxincomputing-com.20200927.dkim.feishu.cn header.b=hz6YjGNi; arc=none smtp.client-ip=101.45.255.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=lanxincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lanxincomputing.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lanxincomputing-com.20200927.dkim.feishu.cn header.i=@lanxincomputing-com.20200927.dkim.feishu.cn header.b="hz6YjGNi" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=lanxincomputing-com.20200927.dkim.feishu.cn; t=1750836928; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=CEUqe5ahfZFpVFJnOYxZcTEDjpo1QaA063NLvGo/wqE=; b=hz6YjGNig7eir5JJNBJsWhz7G9+wpKwt8UlaFU79X89L6GpOiSyzvuf32pK1V9vvwjB3Qt KPKBzGpeDb+FuaXRkLsJbFzvWj1WlJF75YEPuxkc3daX7jycdOkOrLvnZ6d4qt6TFVH24l 3S9PSmysMW09EnhRQRbiLBH+frZoK4jX7ycrLpeFfqnv9VYwt0b9mbehg0qfTRAWzb2Kdr bADv6vpRYJC1RRR+Nt5d/pS1lGSK/sKrNYxKUX59TJpGTBM0uLRp4Z6otu/+fhfgQ9eu3Y wZIbYAOcmBIG0igzKMzXAojtTnDFHUKjHACXjfV+iOYEScs8YIMRdLloKCA5mw== From: "Nutty Liu" Content-Language: en-US To: "Anup Patel" , "Atish Patra" Cc: "Palmer Dabbelt" , "Paul Walmsley" , "Alexandre Ghiti" , "Andrew Jones" , "Anup Patel" , , , , , "Atish Patra" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 User-Agent: Mozilla Thunderbird Content-Transfer-Encoding: 7bit Date: Wed, 25 Jun 2025 15:35:23 +0800 Message-Id: <794a81fa-41d5-4b1e-816f-6d63b883f935@lanxincomputing.com> X-Original-From: Nutty Liu Subject: Re: [PATCH v3 04/12] RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with KVM_REQ_TLB_FLUSH X-Lms-Return-Path: In-Reply-To: <20250618113532.471448-5-apatel@ventanamicro.com> Received: from [127.0.0.1] ([139.226.59.215]) by smtp.feishu.cn with ESMTPS; Wed, 25 Jun 2025 15:35:24 +0800 References: <20250618113532.471448-1-apatel@ventanamicro.com> <20250618113532.471448-5-apatel@ventanamicro.com> On 6/18/2025 7:35 PM, Anup Patel wrote: > The KVM_REQ_HFENCE_GVMA_VMID_ALL is same as KVM_REQ_TLB_FLUSH so > to avoid confusion let's replace KVM_REQ_HFENCE_GVMA_VMID_ALL with > KVM_REQ_TLB_FLUSH. Also, rename kvm_riscv_hfence_gvma_vmid_all_process() > to kvm_riscv_tlb_flush_process(). > > Reviewed-by: Atish Patra > Signed-off-by: Anup Patel > --- > arch/riscv/include/asm/kvm_host.h | 4 ++-- > arch/riscv/kvm/tlb.c | 8 ++++---- > arch/riscv/kvm/vcpu.c | 8 ++------ > 3 files changed, 8 insertions(+), 12 deletions(-) > > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h > index 8aa705ac75a5..ff1f76d6f177 100644 > --- a/arch/riscv/include/asm/kvm_host.h > +++ b/arch/riscv/include/asm/kvm_host.h > @@ -37,7 +37,6 @@ > #define KVM_REQ_UPDATE_HGATP KVM_ARCH_REQ(2) > #define KVM_REQ_FENCE_I \ > KVM_ARCH_REQ_FLAGS(3, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) > -#define KVM_REQ_HFENCE_GVMA_VMID_ALL KVM_REQ_TLB_FLUSH > #define KVM_REQ_HFENCE_VVMA_ALL \ > KVM_ARCH_REQ_FLAGS(4, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) > #define KVM_REQ_HFENCE \ > @@ -331,8 +330,9 @@ void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, > unsigned long order); > void kvm_riscv_local_hfence_vvma_all(unsigned long vmid); > > +void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu); > + > void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu); > -void kvm_riscv_hfence_gvma_vmid_all_process(struct kvm_vcpu *vcpu); > void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu); > void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu); > > diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c > index b3461bfd9756..da98ca801d31 100644 > --- a/arch/riscv/kvm/tlb.c > +++ b/arch/riscv/kvm/tlb.c > @@ -162,7 +162,7 @@ void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu) > local_flush_icache_all(); > } > > -void kvm_riscv_hfence_gvma_vmid_all_process(struct kvm_vcpu *vcpu) > +void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu) > { > struct kvm_vmid *v = &vcpu->kvm->arch.vmid; > unsigned long vmid = READ_ONCE(v->vmid); > @@ -342,14 +342,14 @@ void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm, > data.size = gpsz; > data.order = order; > make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE, > - KVM_REQ_HFENCE_GVMA_VMID_ALL, &data); > + KVM_REQ_TLB_FLUSH, &data); > } > > void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm, > unsigned long hbase, unsigned long hmask) > { > - make_xfence_request(kvm, hbase, hmask, KVM_REQ_HFENCE_GVMA_VMID_ALL, > - KVM_REQ_HFENCE_GVMA_VMID_ALL, NULL); > + make_xfence_request(kvm, hbase, hmask, KVM_REQ_TLB_FLUSH, > + KVM_REQ_TLB_FLUSH, NULL); > } > > void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm, > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index a2dd4161e5a4..6eb11c913b13 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -721,12 +721,8 @@ static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) > if (kvm_check_request(KVM_REQ_FENCE_I, vcpu)) > kvm_riscv_fence_i_process(vcpu); > > - /* > - * The generic KVM_REQ_TLB_FLUSH is same as > - * KVM_REQ_HFENCE_GVMA_VMID_ALL > - */ > - if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu)) > - kvm_riscv_hfence_gvma_vmid_all_process(vcpu); > + if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) > + kvm_riscv_tlb_flush_process(vcpu); > > if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu)) > kvm_riscv_hfence_vvma_all_process(vcpu); Reviewed-by: Nutty Liu Thanks, Nutty