From: Baolu Lu <baolu.lu@linux.intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Jason Gunthorpe <jgg@ziepe.ca>
Cc: baolu.lu@linux.intel.com,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/1] iommu/vt-d: Omit devTLB invalidation requests when TES=0
Date: Tue, 14 Nov 2023 12:54:46 +0800 [thread overview]
Message-ID: <79b2f656-6342-4f46-a4cf-fe8152f1c67f@linux.intel.com> (raw)
In-Reply-To: <BN9PR11MB52761EDB3AE90DE87661A3C28CB2A@BN9PR11MB5276.namprd11.prod.outlook.com>
On 11/14/23 12:45 PM, Tian, Kevin wrote:
>> From: Baolu Lu <baolu.lu@linux.intel.com>
>> Sent: Tuesday, November 14, 2023 11:14 AM
>>
>> On 11/14/23 11:14 AM, Tian, Kevin wrote:
>>>> From: Lu Baolu<baolu.lu@linux.intel.com>
>>>> Sent: Tuesday, November 14, 2023 9:11 AM
>>>>
>>>> The latest VT-d spec indicates that when remapping hardware is disabled
>>>> (TES=0 in Global Status Register), upstream ATS Invalidation Completion
>>>> requests are treated as UR (Unsupported Request).
>>>>
>>>> Consequently, the spec recommends in section 4.3 Handling of Device-TLB
>>>> Invalidations that software refrain from submitting any Device-TLB
>>>> invalidation requests when address remapping hardware is disabled.
>>>>
>>>> Verify address remapping hardware is enabled prior to submitting Device-
>>>> TLB invalidation requests.
>>>>
>>>> Fixes: 792fb43ce2c9 ("iommu/vt-d: Enable Intel IOMMU scalable mode by
>>>> default")
>>>> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>
>>>> ---
>>>> drivers/iommu/intel/dmar.c | 18 ++++++++++++++++++
>>>> 1 file changed, 18 insertions(+)
>>>>
>>>> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
>>>> index a3414afe11b0..23cb80d62a9a 100644
>>>> --- a/drivers/iommu/intel/dmar.c
>>>> +++ b/drivers/iommu/intel/dmar.c
>>>> @@ -1522,6 +1522,15 @@ void qi_flush_dev_iotlb(struct intel_iommu
>>>> *iommu, u16 sid, u16 pfsid,
>>>> {
>>>> struct qi_desc desc;
>>>>
>>>> + /*
>>>> + * VT-d spec, section 4.3:
>>>> + *
>>>> + * Software is recommended to not submit any Device-TLB
>>>> invalidation
>>>> + * requests while address remapping hardware is disabled.
>>>> + */
>>>> + if (!(iommu->gcmd & DMA_GCMD_TE))
>>>> + return;
>>>> +
>>> Is it a valid case to see such request when the iommu is disabled?
>>> If not then let's add a WARN.
>>
>> There might be valid cases. The VT-d translation is turned on after all
>> devices get probed.
>>
>
> but I didn't get why there will be actual mapping changes before
> vtd translation is enabled...
For an example, in iommu_create_device_direct_mappings(),
iommu_flush_iotlb_all() is called after direct mappings are created.
Best regards,
baolu
next prev parent reply other threads:[~2023-11-14 4:59 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-14 1:10 [PATCH 1/1] iommu/vt-d: Support enforce_cache_coherency only for empty domains Lu Baolu
2023-11-14 1:10 ` [PATCH 1/1] iommu/vt-d: Omit devTLB invalidation requests when TES=0 Lu Baolu
2023-11-14 3:14 ` Tian, Kevin
2023-11-14 3:13 ` Baolu Lu
2023-11-14 4:45 ` Tian, Kevin
2023-11-14 4:54 ` Baolu Lu [this message]
2023-11-14 5:31 ` Tian, Kevin
2023-11-29 20:10 ` Jason Gunthorpe
2023-11-30 4:06 ` Baolu Lu
2023-11-30 12:15 ` Jason Gunthorpe
2023-11-14 1:10 ` [PATCH 1/1] iommu/vt-d: Disable PCI ATS in legacy passthrough mode Lu Baolu
2023-11-14 3:14 ` Tian, Kevin
2023-11-16 7:35 ` Baolu Lu
2023-11-16 8:24 ` Tian, Kevin
2023-11-17 1:09 ` Baolu Lu
2023-11-17 2:22 ` Tian, Kevin
2023-11-29 20:13 ` Jason Gunthorpe
2023-11-30 5:44 ` Baolu Lu
2023-11-30 16:18 ` Jason Gunthorpe
2023-11-14 1:10 ` [PATCH 1/1] iommu/vt-d: Make context clearing consistent with context mapping Lu Baolu
2023-11-14 3:20 ` Tian, Kevin
2023-11-14 3:22 ` Baolu Lu
2023-11-14 4:46 ` Tian, Kevin
2023-11-14 3:16 ` [PATCH 1/1] iommu/vt-d: Support enforce_cache_coherency only for empty domains Tian, Kevin
2023-11-29 20:08 ` Jason Gunthorpe
2023-11-30 3:48 ` Baolu Lu
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