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Thu, 04 Sep 2025 22:17:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF/HudJkVHY47aTTdSdxbVjhGZ0iA7XAdq3M3NzhR8STMn+juzLVlL0XwOIV5uAOZ5kdH1N5A== X-Received: by 2002:a17:903:1a67:b0:24c:b83f:c6bc with SMTP id d9443c01a7336-24cb83fcae1mr93316105ad.56.1757049469919; Thu, 04 Sep 2025 22:17:49 -0700 (PDT) Received: from [10.218.42.132] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-24b1f3205cdsm85944905ad.90.2025.09.04.22.17.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Sep 2025 22:17:49 -0700 (PDT) Message-ID: <79d44c24-d853-4128-b966-8a25aaefad73@oss.qualcomm.com> Date: Fri, 5 Sep 2025 10:47:42 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 5/5] PCI: qcom: Add support for ECAM feature To: Bjorn Helgaas Cc: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Manivannan Sadhasivam , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Jingoo Han , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com References: <20250903201233.GA1216782@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20250903201233.GA1216782@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: BRh9RJTJNmKvJoMdasJGNuPLttKNt2G1 X-Authority-Analysis: v=2.4 cv=Jt/xrN4C c=1 sm=1 tr=0 ts=68ba7280 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=qonHfBBtBxQ77LOI7bEA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: BRh9RJTJNmKvJoMdasJGNuPLttKNt2G1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAwMSBTYWx0ZWRfX9tuuTuUJrje3 Mokvbp0XYdcAeqPxl/+k8O8KcvqfoDSLh4zngOhwgR73lcYv236nvVoIbcz2Lj7zrgefMzWW6ww 2UZPXeeUJ7q6G9UQ4yBwD510T4n2nKqXm0VB/uLElMb9PsGICeB3hwqib2nsNDpWLpf+R8OdvWF 4Y8ZNwHCgzmtqfr45dQ2A9t4CwNeyjwo2sNN2Wkr7BgkzM7PULediAXSwiRne2JWh+9UigbtYbq Fsz4oJNEQqIzcwzdokEAeNdSUIuWX7+DPEZyTPFCeFrtpPZJFHaivGSe3z0hToE6OCovqD6lGYX 3LlmiiaiSAh6pm2aSJHVBk6L8hY2A/DI1jHqaLstcrxBFhdeVRVyChXYMlU5S8gicZ8jJQJR6FZ 6uqwhUzg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-05_01,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300001 On 9/4/2025 1:42 AM, Bjorn Helgaas wrote: > On Thu, Aug 28, 2025 at 01:04:26PM +0530, Krishna Chaitanya Chundru wrote: >> The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register >> gives us the offset from which ELBI starts. So override ELBI with the >> offset from PARF_SLV_DBI_ELBI and cfg win to map these regions. >> >> On root bus, we have only the root port. Any access other than that >> should not go out of the link and should return all F's. Since the iATU >> is configured for the buses which starts after root bus, block the >> transactions starting from function 1 of the root bus to the end of >> the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going >> outside the link through ECAM blocker through PARF registers. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 70 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 70 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 5092752de23866ef95036bb3f8fae9bb06e8ea1e..8f3c86c77e2604fd7826083f63b66b4cb62a341d 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -55,6 +55,7 @@ >> #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 >> #define PARF_Q2A_FLUSH 0x1ac >> #define PARF_LTSSM 0x1b0 >> +#define PARF_SLV_DBI_ELBI 0x1b4 >> #define PARF_INT_ALL_STATUS 0x224 >> #define PARF_INT_ALL_CLEAR 0x228 >> #define PARF_INT_ALL_MASK 0x22c >> @@ -64,6 +65,16 @@ >> #define PARF_DBI_BASE_ADDR_V2_HI 0x354 >> #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 >> #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c >> +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 >> +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 >> +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 >> +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c >> +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 >> +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 >> +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 >> +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c >> +#define PARF_ECAM_BASE 0x380 >> +#define PARF_ECAM_BASE_HI 0x384 >> #define PARF_NO_SNOOP_OVERRIDE 0x3d4 >> #define PARF_ATU_BASE_ADDR 0x634 >> #define PARF_ATU_BASE_ADDR_HI 0x638 >> @@ -87,6 +98,7 @@ >> >> /* PARF_SYS_CTRL register fields */ >> #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) >> +#define PCIE_ECAM_BLOCKER_EN BIT(26) >> #define MST_WAKEUP_EN BIT(13) >> #define SLV_WAKEUP_EN BIT(12) >> #define MSTR_ACLK_CGC_DIS BIT(10) >> @@ -134,6 +146,9 @@ >> /* PARF_LTSSM register fields */ >> #define LTSSM_EN BIT(8) >> >> +/* PARF_SLV_DBI_ELBI */ >> +#define SLV_DBI_ELBI_ADDR_BASE GENMASK(11, 0) >> + >> /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ >> #define PARF_INT_ALL_LINK_UP BIT(13) >> #define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23) >> @@ -317,6 +332,48 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) >> qcom_perst_assert(pcie, false); >> } >> >> +static void qcom_pci_config_ecam(struct dw_pcie_rp *pp) >> +{ >> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> + struct qcom_pcie *pcie = to_qcom_pcie(pci); >> + u64 addr, addr_end; >> + u32 val; >> + >> + /* Set the ECAM base */ >> + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); >> + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); >> + >> + /* >> + * The only device on root bus is the Root Port. Any access to the PCIe >> + * region will go outside the PCIe link. As part of enumeration the PCI >> + * sw can try to read to vendor ID & device ID with different device >> + * number and function number under root bus. As any access other than >> + * root bus, device 0, function 0, should not go out of the link and >> + * should return all F's. Since the iATU is configured for the buses >> + * which starts after root bus, block the transactions starting from >> + * function 1 of the root bus to the end of the root bus (i.e from >> + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link. >> + */ >> + addr = pci->dbi_phys_addr + SZ_4K; >> + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); >> + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); >> + >> + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); >> + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); >> + >> + addr_end = pci->dbi_phys_addr + SZ_1M - 1; >> + >> + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); >> + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI); >> + >> + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); >> + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI); >> + >> + val = readl_relaxed(pcie->parf + PARF_SYS_CTRL); >> + val |= PCIE_ECAM_BLOCKER_EN; >> + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL); >> +} >> + >> static int qcom_pcie_start_link(struct dw_pcie *pci) >> { >> struct qcom_pcie *pcie = to_qcom_pcie(pci); >> @@ -326,6 +383,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) >> qcom_pcie_common_set_16gt_lane_margining(pci); >> } >> >> + if (pci->pp.ecam_enabled) >> + qcom_pci_config_ecam(&pci->pp); >> + >> /* Enable Link Training state machine */ >> if (pcie->cfg->ops->ltssm_enable) >> pcie->cfg->ops->ltssm_enable(pcie); >> @@ -1314,6 +1374,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >> { >> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> struct qcom_pcie *pcie = to_qcom_pcie(pci); >> + u16 offset; >> int ret; >> >> qcom_ep_reset_assert(pcie); >> @@ -1322,6 +1383,15 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >> if (ret) >> return ret; >> >> + if (pp->ecam_enabled) { >> + /* >> + * Override ELBI when ECAM is enabled, as when ECAM >> + * is enabled ELBI moves along with the dbi config space. >> + */ >> + offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI)); >> + pci->elbi_base = pci->dbi_base + offset; > > This looks like there might be a bisection hole between this patch and > the previous patch that enables ECAM in the DWC core? Obviously I > would want to avoid a bisection hole. > > What happens to qcom ELBI accesses between these two patches? It > looks like they would go to the wrong address until this elbi_base > update. > > Is this connection between DBI and ELBI specific to qcom, or might > other users of ELBI (only exynos, I guess) need a similar update to > elbi_base? > This is specific to QCOM only, with the commit 10ba0854c5e61 ("PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region") The DBI address can moved to upper region of the PCIe region. When DBI is moved ELBI also moves along with it. So if this patch is not present elbi will not point to correct ELBI address. - Krishna Chaitanya. >> + } >> + >> ret = qcom_pcie_phy_power_on(pcie); >> if (ret) >> goto err_deinit; >> >> -- >> 2.34.1 >>