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[192.35.156.11]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b7127afff91sm11487662a12.13.2025.10.28.15.15.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Oct 2025 15:15:35 -0700 (PDT) Message-ID: <7ae01221-868e-d5dc-4297-8006a69e7a7c@oss.qualcomm.com> Date: Tue, 28 Oct 2025 15:15:33 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v6 6/8] phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings Content-Language: en-US To: Dmitry Baryshkov Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Abel Vesa , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251024-glymur_usb-v6-0-471fa39ff857@oss.qualcomm.com> <20251024-glymur_usb-v6-6-471fa39ff857@oss.qualcomm.com> From: Wesley Cheng In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ewWMhQ1NWK4uar5Tl7fpehPcmXC_Lsy_ X-Proofpoint-GUID: ewWMhQ1NWK4uar5Tl7fpehPcmXC_Lsy_ X-Authority-Analysis: v=2.4 cv=avi/yCZV c=1 sm=1 tr=0 ts=69014089 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZdW6uxA9NKXbfdqeeS2OGA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=wlTfea_xsf4MiaLh13MA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDI4MDE4NyBTYWx0ZWRfXz5RHpu3ZJEGt 7ldKDXYNRISv+iwZwXrgsHm9nP2mKhv1zwVLtm9GtlQbonyyMuHiPwog8rJe9d37uZe0P15B9ww y8tuoo4jHrxamio1UVja8/oZI1EUMTdFTzMBmIiO3xtogAuRasrd5v0Jz6ywonZIc2c9iYP9YKZ wfTpaXzrXQIx7tcw0pmnyH1pGQN2aSe7/bhx30J1tKReqPDad6DaYTT80cZyvMQf9u3cOFUViDv 2bpG6PRtwUuwg6MsKIFHP0rg+17DthRTVSFvn75yAU/DuvcwPPnalI4Mx3QeoaqEdFl3a/SUbIw +94ddT139ti3HYfBGVcDlLOfitIrs88OlZvDK106j5lvSicFQxQJOldBbyGPqy8kYPzjyX8L4Ya TFzDmU6LC1lxhKTKBAXq7laPDc4ZQQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-28_08,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 adultscore=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510280187 On 10/27/2025 7:21 AM, Dmitry Baryshkov wrote: > On Fri, Oct 24, 2025 at 05:47:44PM -0700, Wesley Cheng wrote: >> For SuperSpeed USB to work properly, there is a set of HW settings that >> need to be programmed into the USB blocks within the QMP PHY. Ensure that >> these settings follow the latest settings mentioned in the HW programming >> guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some >> new ways to define certain registers, such as the replacement of TXA/RXA >> and TXB/RXB register sets. This was replaced with the LALB register set. >> >> There are also some PHY init updates to modify the PCS MISC register space. >> Without these, the QMP PHY PLL locking fails. >> >> Signed-off-by: Wesley Cheng >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 288 ++++++++++ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h | 17 + >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h | 12 + >> .../phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h | 639 +++++++++++++++++++++ >> drivers/phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h | 33 ++ >> .../qualcomm/phy-qcom-qmp-usb43-qserdes-com-v8.h | 224 ++++++++ >> drivers/phy/qualcomm/phy-qcom-qmp.h | 2 + >> 7 files changed, 1215 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >> index 1caa1fb6a8c7..d1534ed7200b 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >> @@ -30,9 +30,11 @@ >> >> #include "phy-qcom-qmp.h" >> #include "phy-qcom-qmp-pcs-aon-v6.h" >> +#include "phy-qcom-qmp-pcs-aon-v8.h" >> #include "phy-qcom-qmp-pcs-misc-v3.h" >> #include "phy-qcom-qmp-pcs-misc-v4.h" >> #include "phy-qcom-qmp-pcs-misc-v5.h" >> +#include "phy-qcom-qmp-pcs-misc-v8.h" >> #include "phy-qcom-qmp-pcs-usb-v4.h" >> #include "phy-qcom-qmp-pcs-usb-v5.h" >> #include "phy-qcom-qmp-pcs-usb-v6.h" >> @@ -46,6 +48,8 @@ >> #include "phy-qcom-qmp-dp-phy-v5.h" >> #include "phy-qcom-qmp-dp-phy-v6.h" >> >> +#include "phy-qcom-qmp-usb43-pcs-v8.h" >> + >> /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ >> /* DP PHY soft reset */ >> #define SW_DPPHY_RESET BIT(0) >> @@ -97,6 +101,7 @@ enum qphy_reg_layout { >> QPHY_TX_HIGHZ_DRVR_EN, >> QPHY_TX_TRANSCEIVER_BIAS_EN, >> >> + QPHY_AON_TOGGLE_ENABLE, >> /* Keep last to ensure regs_layout arrays are properly initialized */ >> QPHY_LAYOUT_SIZE >> }; >> @@ -259,6 +264,236 @@ static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { >> [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN, >> }; >> >> +static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = { >> + [QPHY_SW_RESET] = QPHY_V6_N4_PCS_SW_RESET, >> + [QPHY_START_CTRL] = QPHY_V6_N4_PCS_START_CONTROL, >> + [QPHY_PCS_STATUS] = QPHY_V6_N4_PCS_PCS_STATUS1, >> + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL, > > V8 PHY should not be using V6 register offsets. > >> + >> + /* In PCS_USB */ >> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, >> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, >> + >> + [QPHY_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_TOGGLE_ENABLE, >> + >> + [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, >> + [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, >> + [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, >> + [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, >> + >> + [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, >> + [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, >> + >> + [QPHY_TX_TX_POL_INV] = QSERDES_V6_N4_TX_TX_POL_INV, >> + [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_N4_TX_TX_DRV_LVL, >> + [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL, >> + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN, >> + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN, >> +}; >> + >> @@ -2528,6 +2784,27 @@ static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = { >> .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), >> }; >> >> +static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = { >> + .offsets = &qmp_combo_usb43dp_offsets_v8, >> + >> + .serdes_tbl = glymur_usb43dp_serdes_tbl, >> + .serdes_tbl_num = ARRAY_SIZE(glymur_usb43dp_serdes_tbl), >> + .tx_tbl = glymur_usb43dp_lalb_tbl, >> + .tx_tbl_num = ARRAY_SIZE(glymur_usb43dp_lalb_tbl), >> + .pcs_tbl = glymur_usb43dp_pcs_tbl, >> + .pcs_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_tbl), >> + .pcs_usb_tbl = glymur_usb43dp_pcs_usb_tbl, >> + .pcs_usb_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_usb_tbl), >> + .pcs_misc_tbl = glymur_usb43dp_pcs_misc_tbl, >> + .pcs_misc_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_misc_tbl), > > DP tables are missing. > Hi Dmitry, I think I discussed this with Abel on the previous patch revision. At the moment I did not add support for DP, so we shouldn't add the tables, unless you think we should still have placeholder? Thanks Wesley Cheng >> + >> + .regs = qmp_v8_n3_usb43dpphy_regs_layout, >> + .reset_list = msm8996_usb3phy_reset_l, >> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), >> + .vreg_list = qmp_phy_vreg_refgen, >> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_refgen), >> +}; >> + >> static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) >> { >> const struct qmp_phy_cfg *cfg = qmp->cfg; >> @@ -3024,6 +3301,7 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) >> { >> const struct qmp_phy_cfg *cfg = qmp->cfg; >> void __iomem *com = qmp->com; >> + void __iomem *pcs_aon = qmp->pcs_aon; >> int ret; >> u32 val; >> >> @@ -3059,6 +3337,10 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) >> SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | >> SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); >> >> + /* override hardware control for reset of qmp phy */ >> + if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) >> + qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1); >> + >> /* Use software based port select and switch on typec orientation */ >> val = SW_PORTSELECT_MUX; >> if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) >> @@ -3236,6 +3518,8 @@ static int qmp_combo_usb_power_on(struct phy *phy) >> qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); >> >> qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); >> + qmp_configure(qmp->dev, qmp->pcs_misc, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); >> + > > Extra empty line. > >> >> if (pcs_usb) >> qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, >