* [PATCH v2] arm64: dts: qcom: sa8775p: Mark APPS and PCIe SMMUs as DMA coherent
@ 2024-07-23 7:59 Qingqing Zhou
2024-07-23 8:12 ` Krzysztof Kozlowski
0 siblings, 1 reply; 3+ messages in thread
From: Qingqing Zhou @ 2024-07-23 7:59 UTC (permalink / raw)
To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt, ahalaney,
manivannan.sadhasivam
Cc: linux-arm-msm, devicetree, linux-kernel, stable, Qingqing Zhou
The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
mark the APPS and PCIe ones as well.
Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
Fixes: 2dba7a613a6e ("arm64: dts: qcom: sa8775p: add the pcie smmu node")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
---
Changes in v2:
- Add the Fixes tags.
- Update the commit message.
- Link to v1: https://lore.kernel.org/lkml/20240715071649.25738-1-quic_qqzhou@quicinc.com/
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 23f1b2e5e624..95691ab58a23 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3070,6 +3070,7 @@
reg = <0x0 0x15000000 0x0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <2>;
+ dma-coherent;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
@@ -3208,6 +3209,7 @@
reg = <0x0 0x15200000 0x0 0x80000>;
#iommu-cells = <2>;
#global-interrupts = <2>;
+ dma-coherent;
interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: sa8775p: Mark APPS and PCIe SMMUs as DMA coherent
2024-07-23 7:59 [PATCH v2] arm64: dts: qcom: sa8775p: Mark APPS and PCIe SMMUs as DMA coherent Qingqing Zhou
@ 2024-07-23 8:12 ` Krzysztof Kozlowski
2024-07-23 9:51 ` Qingqing Zhou
0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Kozlowski @ 2024-07-23 8:12 UTC (permalink / raw)
To: Qingqing Zhou, andersson, konrad.dybcio, robh, krzk+dt, conor+dt,
ahalaney, manivannan.sadhasivam
Cc: linux-arm-msm, devicetree, linux-kernel, stable
On 23/07/2024 09:59, Qingqing Zhou wrote:
> The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
> mark the APPS and PCIe ones as well.
>
> Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
> Fixes: 2dba7a613a6e ("arm64: dts: qcom: sa8775p: add the pcie smmu node")
>
For the future: there is never, never a line break between tags.
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: sa8775p: Mark APPS and PCIe SMMUs as DMA coherent
2024-07-23 8:12 ` Krzysztof Kozlowski
@ 2024-07-23 9:51 ` Qingqing Zhou
0 siblings, 0 replies; 3+ messages in thread
From: Qingqing Zhou @ 2024-07-23 9:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, andersson, konrad.dybcio, robh, krzk+dt,
conor+dt, ahalaney, manivannan.sadhasivam
Cc: linux-arm-msm, devicetree, linux-kernel, stable
在 7/23/2024 4:12 PM, Krzysztof Kozlowski 写道:
> On 23/07/2024 09:59, Qingqing Zhou wrote:
>> The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
>> mark the APPS and PCIe ones as well.
>>
>> Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
>> Fixes: 2dba7a613a6e ("arm64: dts: qcom: sa8775p: add the pcie smmu node")
>>
>
> For the future: there is never, never a line break between tags.
OK, thanks for reviewing and sorry for this, will update in next version.
>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-07-23 7:59 [PATCH v2] arm64: dts: qcom: sa8775p: Mark APPS and PCIe SMMUs as DMA coherent Qingqing Zhou
2024-07-23 8:12 ` Krzysztof Kozlowski
2024-07-23 9:51 ` Qingqing Zhou
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