From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 998D7C433DB for ; Fri, 5 Feb 2021 18:01:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 53FF164DE8 for ; Fri, 5 Feb 2021 18:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232917AbhBEQSi (ORCPT ); Fri, 5 Feb 2021 11:18:38 -0500 Received: from mail29.static.mailgun.info ([104.130.122.29]:44823 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231912AbhBEQPG (ORCPT ); Fri, 5 Feb 2021 11:15:06 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1612547823; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=yjcgfI0QYGg6Rxk3COL/nMdKpQeHfQgSqPtTICgLZeo=; b=JzvvsqcsKuYBVRx6AK4lA3DJAAhK/SCU5rxBHYX3L2Yxqo0hqRwsoITubau0c/vKK0F0Hn5K llefbsCGuLHtcfxaEC55n93dIHURIwn5zfxYBQlX/SOGz583pmOX6f2KabwUKe2h5i6Tx1ve 5k2DQ3bFZ7RTycPEFL3QV2zs7kg= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-west-2.postgun.com with SMTP id 601d86d234db06ef79ede78c (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 05 Feb 2021 17:56:34 GMT Sender: mdalam=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 1F5B7C43465; Fri, 5 Feb 2021 17:56:34 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: mdalam) by smtp.codeaurora.org (Postfix) with ESMTPSA id 44975C43461; Fri, 5 Feb 2021 17:56:33 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 05 Feb 2021 23:26:33 +0530 From: mdalam@codeaurora.org To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, boris.brezillon@collabora.com, manivannan.sadhasivam@linaro.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: sricharan@codeaurora.org Subject: Re: [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset In-Reply-To: <1612037236-7954-1-git-send-email-mdalam@codeaurora.org> References: <1612037236-7954-1-git-send-email-mdalam@codeaurora.org> Message-ID: <7ca35f62c4d3ba7833e192cab3a2701d@codeaurora.org> X-Sender: mdalam@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-01-31 01:37, Md Sadre Alam wrote: > This change will remove unused register name macro NAND_DEV1_ECC_CFG. > Since this register was only available in QPIC version 1.4.20 ipq40xx > and it was not used. In QPIC version 1.5 on wards this register got > removed.In QPIC version 2.0 0x2c offset is updated with register > NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN > with offset 0x2c. > > Signed-off-by: Md Sadre Alam Ping! Is any additional info needed for this patch ? > --- > drivers/mtd/nand/raw/qcom_nandc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c > b/drivers/mtd/nand/raw/qcom_nandc.c > index 9484be8..c238a35 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -27,7 +27,7 @@ > #define NAND_DEV0_CFG0 0x20 > #define NAND_DEV0_CFG1 0x24 > #define NAND_DEV0_ECC_CFG 0x28 > -#define NAND_DEV1_ECC_CFG 0x2c > +#define NAND_AUTO_STATUS_EN 0x2c > #define NAND_DEV1_CFG0 0x30 > #define NAND_DEV1_CFG1 0x34 > #define NAND_READ_ID 0x40