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Tue, 05 May 2026 05:40:20 -0700 (PDT) Received: from [192.168.88.32] ([212.105.155.47]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a8ebb2f32sm353251655e9.13.2026.05.05.05.40.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 May 2026 05:40:19 -0700 (PDT) Message-ID: <7d657e09-1037-4f0d-b0f6-70228a4acccd@redhat.com> Date: Tue, 5 May 2026 14:40:18 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v2 3/3] net: eth: fbnic: Add pma read and write access To: mike.marciniszyn@gmail.com, Alexander Duyck , Jakub Kicinski , kernel-team@meta.com, Andrew Lunn , "David S. Miller" , Eric Dumazet , Heiner Kallweit , Russell King , Jacob Keller , Mohsin Bashir , Lee Trager , Andrew Lunn Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260430150802.3521-1-mike.marciniszyn@gmail.com> <20260430150802.3521-4-mike.marciniszyn@gmail.com> Content-Language: en-US From: Paolo Abeni In-Reply-To: <20260430150802.3521-4-mike.marciniszyn@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 4/30/26 5:08 PM, mike.marciniszyn@gmail.com wrote: > From: "Mike Marciniszyn (Meta)" > > Document the MDIO interface topology with an ASCII diagram > showing the MAC, PCS (MMD 3), FEC, Separated PMA (MMD 8), and PMD > (MMD 1) blocks and their interconnects. The diagram illustrates how > 4 lanes connect the MAC through PCS, FEC, and PMA, then narrow to > 2 lanes at the PMD. > > The c45 read and write routines are enhanced to support > read and write of the separated PMA for the fbnic. > > Co-developed-by: Alexander Duyck > Signed-off-by: Alexander Duyck > Signed-off-by: Mike Marciniszyn (Meta) > --- > v2: > - no changes > v1: https://lore.kernel.org/all/20260428172810.175077-5-mike.marciniszyn@gmail.com/ > > drivers/net/ethernet/meta/fbnic/fbnic_csr.h | 1 + > drivers/net/ethernet/meta/fbnic/fbnic_mdio.c | 71 ++++++++++++++++++++ > 2 files changed, 72 insertions(+) > > diff --git a/drivers/net/ethernet/meta/fbnic/fbnic_csr.h b/drivers/net/ethernet/meta/fbnic/fbnic_csr.h > index 81794bd326e1..64b958df7774 100644 > --- a/drivers/net/ethernet/meta/fbnic/fbnic_csr.h > +++ b/drivers/net/ethernet/meta/fbnic/fbnic_csr.h > @@ -805,6 +805,7 @@ enum { > #define FBNIC_CSR_END_PCS 0x10668 /* CSR section delimiter */ > > #define FBNIC_CSR_START_RSFEC 0x10800 /* CSR section delimiter */ > +#define FBNIC_RSFEC_CONTROL(n) (0x10800 + 8 * (n)) /* 0x42000 + 32*n */ Sashiko says: --- With the introduction of the RSFEC memory space at 0x10800, does the bounds check in fbnic_mdio_write_pcs() need to be updated to prevent clobbering these new registers? While not introduced by this patch, fbnic_mdio_write_pcs() currently contains: /* Allow access to both halves of PCS for 50R2 config */ if (addr > 2) return; When addr is 2, FBNIC_PCS_PAGE(2) evaluates to 0x10000 + 0x400 * 2, which is 0x10800. Since this overlaps with FBNIC_CSR_START_RSFEC, an MDIO write to MMD 3 (PCS) at address 2 could silently overwrite the newly managed RSFEC control registers. The read function fbnic_mdio_read_pcs() correctly uses if (addr >= 2) to prevent this. Should the write function be updated to match? --- Does not look blocking to me, but a follow-up could be needed. /P