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Tue, 05 Aug 2025 05:24:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEmAtlyoCkBTucfFzqAePs0iFp/iqsO9db8iSLJTshnWRKP8i368ShtTr8e0T6Hm+SHVmEG2g== X-Received: by 2002:a05:6300:218e:b0:21f:4ecc:11ab with SMTP id adf61e73a8af0-23df8f93cd1mr16966180637.9.1754396653534; Tue, 05 Aug 2025 05:24:13 -0700 (PDT) Received: from [10.253.39.156] ([114.94.8.21]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b422bb0570bsm11090730a12.54.2025.08.05.05.24.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Aug 2025 05:24:12 -0700 (PDT) Message-ID: <7e4d9dfe-428f-4374-9be7-97123cf36e5a@oss.qualcomm.com> Date: Tue, 5 Aug 2025 20:24:07 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/2] arm64: dts: qcom: Add display support for QCS615 To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xiangxu Yin , Li Liu , Dmitry Baryshkov References: <20250718-add-display-support-for-qcs615-platform-v5-0-8579788ea195@oss.qualcomm.com> <20250718-add-display-support-for-qcs615-platform-v5-1-8579788ea195@oss.qualcomm.com> <1f6fc7ce-5826-4f59-89d7-ac691a3ae785@oss.qualcomm.com> Content-Language: en-US From: Fange Zhang In-Reply-To: <1f6fc7ce-5826-4f59-89d7-ac691a3ae785@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: tf6h7tzuu5enoPAcl1P0hawAQI7W4u2E X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA1MDA5MCBTYWx0ZWRfXzHrxK2MKy8nN /ENiL6xwFFH1A+VfCa73pzOfBhi2m0l3di5WAND9f4UVpxOdBScQ31moqS4GCk12tm50czHIc0M iFqPjnAgvQhmijHStOtiZEt33TJGXrv1qApSFTFeNVwDL4rV9Pt1pcxaF3yVC09ZNOVD2SEG6aH Zk6KgmHmCaWb7Rs8DrEfI4XrkEJN6pIu2coBUv5i8Q9/sk9mDzdIMDP+ezvihlHfO5pl/n6uBwc tK3u+odU4vuyUC4P8VVWVvCWEp5lN+J248gtiEyZDeIoUdASKZ34coQb6xtI0YBMnYLyP3Wk0SY chBG5O78EF70e6ykTdWGF+IkzFXufmUzEqzSdUCTs6tmWEARgAoUGgkmtYRahAs5/4gdGHS23oL Jx+f0OjNBBPbHSeqEZbGHYikMCPqkPrIH4/6mOmxiMoN8SR6+/7rErh8vTJ+kY1Ock0e2y/k X-Proofpoint-GUID: tf6h7tzuu5enoPAcl1P0hawAQI7W4u2E X-Authority-Analysis: v=2.4 cv=a8Mw9VSF c=1 sm=1 tr=0 ts=6891f7ef cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=oI82J1t3JKGWbxmVtl0A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-05_03,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 phishscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508050090 On 7/29/2025 7:17 PM, Konrad Dybcio wrote: > On 7/18/25 2:56 PM, Fange Zhang wrote: >> From: Li Liu >> >> Add display MDSS and DSI configuration for QCS615 platform. >> QCS615 has a DP port, and DP support will be added in a later patch. >> >> Reviewed-by: Dmitry Baryshkov >> Signed-off-by: Li Liu >> Signed-off-by: Fange Zhang >> --- > > [...] > >> + >> + mdss_mdp: display-controller@ae01000 { >> + compatible = "qcom,sm6150-dpu"; >> + reg = <0x0 0x0ae01000 0x0 0x8f000>, >> + <0x0 0x0aeb0000 0x0 0x2008>; >> + reg-names = "mdp", "vbif"; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_CLK>, >> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >> + clock-names = "iface", "bus", "core", "vsync"; > > 1 per line please, everywhere> + Got it will fix it in next patch>> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >> + assigned-clock-rates = <19200000>; > > Is this necessary? test pass without this, so will remove them in next patch> >> + >> + operating-points-v2 = <&mdp_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <0>; > > interrupts-extended Got it, will change it as below in next patch interrupts-extended = <&mdss 0>;> >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; > > Please keep a \n between properties and subnodes will fix it in next patch> >> + dpu_intf0_out: endpoint { >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + dpu_intf1_out: endpoint { >> + remote-endpoint = <&mdss_dsi0_in>; >> + }; >> + }; >> + }; >> + >> + mdp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-19200000 { >> + opp-hz = /bits/ 64 <19200000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-25600000 { >> + opp-hz = /bits/ 64 <25600000>; >> + required-opps = <&rpmhpd_opp_svs>; > > This and the above frequency are missing one zero (i.e. you > have a 10x underclock) Got it, will fix it in next patch> > [...] > >> + mdss_dsi0_phy: phy@ae94400 { >> + compatible = "qcom,sm6150-dsi-phy-14nm"; >> + reg = <0x0 0x0ae94400 0x0 0x100>, >> + <0x0 0x0ae94500 0x0 0x300>, >> + <0x0 0x0ae94800 0x0 0x188>; > > sz = 0x124 Got it, will change 0x188 to 0x124 in next patch> >> + reg-names = "dsi_phy", >> + "dsi_phy_lane", >> + "dsi_pll"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", "ref"; >> + >> + status = "disabled"; >> + }; >> + }; >> + >> dispcc: clock-controller@af00000 { >> compatible = "qcom,qcs615-dispcc"; >> reg = <0 0x0af00000 0 0x20000>; >> >> clocks = <&rpmhcc RPMH_CXO_CLK>, >> - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; >> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, >> + <&mdss_dsi0_phy 0>, >> + <&mdss_dsi0_phy 1>, > > #include Got it, will add the h file and change as below in next patch <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,> > Konrad