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[130.111.218.23]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6fb5a9dbf8csm18549736d6.106.2025.06.17.20.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 20:49:19 -0700 (PDT) From: Vince Weaver X-Google-Original-From: Vince Weaver Date: Tue, 17 Jun 2025 23:49:18 -0400 (EDT) To: "Liang, Kan" cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Subject: Re: [perf] unchecked MSR access error: WRMSR to 0x3f1 In-Reply-To: <574b8701-9676-4aba-a85b-724c979b2efa@linux.intel.com> Message-ID: <7e8bb736-3955-c479-99de-e08efb494bdd@maine.edu> References: <14d3167e-4dad-f68e-822f-21cd86eab873@maine.edu> <574b8701-9676-4aba-a85b-724c979b2efa@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Tue, 17 Jun 2025, Liang, Kan wrote: > The commit 2dc0572f2cef was triggered by the fake event VLBR_EVENT. > But this error should be triggered by the Topdown perf metrics event, > INTEL_TD_METRIC_RETIRING, which uses the idx 48 internally. > > We never support perf metrics events in sampling mode. The PEBS cannot > be enabled in counting mode. So it's weird the cpuc->pebs_enabled has > the idx 48 set. > > The recent change I did for the PEBS is commit e02e9b0374c3 > "perf/x86/intel: Support PEBS counters snapshotting". But it should not > impact the above. > > Could you please help on the below questions? > - It only happens on the p-core, right? how would I tell? I don't think the error message says what CPU it happens on? > - Which kernel base do you use? Is it 6.16-rc2? I was running just before -rc1. I've updated to current git but didn't realize the throttle fix hadn't made it upstream yet so managed to lock up the machine and not sure when I'll be able to get over to reboot it. > - Can this be easily reproduced? probably. It's another thing that's a pain to check because it's a WARN_ONCE I think so I have to reboot in order to see. Even if it's not reproducible the fuzzer usually hits it within a few hours. > Is it possible to bisect the error commit? (Maybe start from the > commit e02e9b0374c3?) Maybe but I'd only like to do that as a last resort as it's a pain to build and reboot kernels on this machine (for secureboot and other reasons). Also I suppose I'd have to manually apply the throttle patch while bisecting. Vince Weaver vincent.weaver@maine.edu