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Thu, 12 Feb 2026 10:52:29 +0100 (CET) Message-ID: <7ec57033-b0d8-4aa5-b23c-a7ab62fd38f4@collabora.com> Date: Thu, 12 Feb 2026 10:52:28 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] soc: mediatek: mtk-mmsys: Add resets for mt8167 To: Luca Leonardo Scorcia , linux-mediatek@lists.infradead.org Cc: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Philipp Zabel , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <0ab331c556d76ddfc7f287d6288c4f60f4ef90c8.1770836190.git.l.scorcia@gmail.com> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <0ab331c556d76ddfc7f287d6288c4f60f4ef90c8.1770836190.git.l.scorcia@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 11/02/26 20:03, Luca Leonardo Scorcia ha scritto: > The mt8167 SoC has 64 MMSYS resets, split in two contiguous 32-bits > registers, MMSYS_SW0_RST_B (0x140) and MMSYS_SW1_RST_B (0x144), as > also stated in the downstream kernel for the Lenovo Smart Clock > in the ddp_reg.h header. > > Signed-off-by: Luca Leonardo Scorcia > --- > drivers/soc/mediatek/mt8167-mmsys.h | 3 +++ > drivers/soc/mediatek/mtk-mmsys.c | 2 ++ > 2 files changed, 5 insertions(+) > > diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h > index eef14083c47b..2d20b21fb0ea 100644 > --- a/drivers/soc/mediatek/mt8167-mmsys.h > +++ b/drivers/soc/mediatek/mt8167-mmsys.h > @@ -18,6 +18,9 @@ > #define MT8167_DSI0_SEL_IN_RDMA0 0x1 > #define MT8167_DSI0_SEL_IN_MASK 0x3 > > +#define MT8167_MMSYS_SW0_RST_B 0x140 > +#define MT8167_MMSYS_SW1_RST_B 0x144 > + > static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { > MMSYS_ROUTE(OVL0, COLOR0, > MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index bb4639ca0b8c..03cbc393f978 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -57,6 +57,8 @@ static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { > .clk_driver = "clk-mt8167-mm", > .routes = mt8167_mmsys_routing_table, > .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), > + .sw0_rst_offset = MT8167_MMSYS_SW0_RST_B, > + .num_resets = 64, Unless you have the full reset table... .rst_tb = (const u8[]) { [MT8167_MMSYS_SW0_RST_B_SMI_COMMON] = MMSYS_RST_NR(0, 0), [MT8167_MMSYS_SW0_RST_B_SMI_LARB] = MMSYS_RST_NR(0, 1), [MT8167_MMSYS_SW0_RST_B_CAM_MDP] = MMSYS_RST_NR(0, 2), [MT8167_MMSYS_SW0_RST_B_MDP_RDMA0] = MMSYS_RST_NR(0, 3), [MT8167_MMSYS_SW0_RST_B_MDP_RSZ0] = MMSYS_RST_NR(0, 4), [MT8167_MMSYS_SW0_RST_B_MDP_RSZ1] = MMSYS_RST_NR(0, 5), [MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0] = MMSYS_RST_NR(0, 6), [MT8167_MMSYS_SW0_RST_B_MDP_WDMA] = MMSYS_RST_NR(0, 7), [MT8167_MMSYS_SW0_RST_B_MDP_WROT0] = MMSYS_RST_NR(0, 8), [MT8167_MMSYS_SW0_RST_B_DISP_DSI0] = MMSYS_RST_NR(0, 22), }, .num_resets = 10, Cheers, Angelo > }; > > static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {