From: Easwar Hariharan <eahariha@linux.microsoft.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Andre Przywara <andre.przywara@arm.com>,
Rob Herring <robh@kernel.org>, Fuad Tabba <tabba@google.com>,
Joey Gouly <joey.gouly@arm.com>,
Kristina Martsenko <kristina.martsenko@arm.com>,
"moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)"
<linux-arm-kernel@lists.infradead.org>,
open list <linux-kernel@vger.kernel.org>,
"open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)"
<kvmarm@lists.linux.dev>
Subject: Re: [RFC PATCH] KVM: arm64: Override Microsoft Azure Cobalt 100 MIDR value with ARM Neoverse N2
Date: Thu, 8 Feb 2024 11:16:15 -0800 [thread overview]
Message-ID: <7ef4b699-0b62-4610-bcd1-68c9d253959c@linux.microsoft.com> (raw)
In-Reply-To: <df731836-04ab-41b9-b317-434a1060ad61@arm.com>
On 2/6/2024 11:54 PM, Anshuman Khandual wrote:
>
> On 2/7/24 01:28, Easwar Hariharan wrote:
>> Several workload optimizations and errata depend on validating that the
>> optimization or errata are applicable to the particular CPU by checking
>> the MIDR_EL1 system register value. With the Microsoft implementer ID
>
> Which is how it should be done.
>
>> for Azure Cobalt 100, the value doesn't match and ~20-25% performance
>> regression is seen in these workloads. Override the Azure Cobalt 100
>> value and replace it with the default ARM Neoverse N2 value that Azure
>> Cobalt 100 is based on.
>
> Why cannot these MIDR values be classified as required and subscribed to
> the existing erratas that is affecting such implementations. Hence these
> work arounds will be triggered as and when applicable. Why then override
> MIDR value instead ?
>
Thanks for the feedback, I will go ahead and add the Azure Cobalt 100 MIDR
value to the range of MIDRs affected by the Neoverse N2 errata. This
patch was a proof of concept to have userspace apply the Neoverse N2
optimizations to Azure Cobalt 100 as well. As Mark mentioned in a sibling
response, this is not an acceptable way to accomplish this.
>>
>> Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com>
>> ---
>> arch/arm64/include/asm/cputype.h | 3 ++-
>> arch/arm64/include/asm/el2_setup.h | 5 +++++
>> arch/arm64/kvm/sys_regs.c | 9 ++++++++-
>> 3 files changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
>> index 7c7493cb571f..0450c6c32377 100644
>> --- a/arch/arm64/include/asm/cputype.h
>> +++ b/arch/arm64/include/asm/cputype.h
>> @@ -262,7 +262,8 @@ is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
>> */
>> static inline u32 __attribute_const__ read_cpuid_id(void)
>> {
>> - return read_cpuid(MIDR_EL1);
>> + return (read_cpuid(MIDR_EL1) == 0x6D0FD490 ? 0x410FD490 :
>> + read_cpuid(MIDR_EL1));
>> }
>>
>> static inline u64 __attribute_const__ read_cpuid_mpidr(void)
>> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
>> index b7afaa026842..502a14e54a31 100644
>> --- a/arch/arm64/include/asm/el2_setup.h
>> +++ b/arch/arm64/include/asm/el2_setup.h
>> @@ -138,6 +138,11 @@
>> .macro __init_el2_nvhe_idregs
>> mrs x0, midr_el1
>> mrs x1, mpidr_el1
>> + ldr x2, =0x6D0FD490
>> + cmp x0, x2
>> + bne .Loverride_cobalt100_\@
>> + ldr x0, =0x410FD490
>> +.Loverride_cobalt100_\@:
>> msr vpidr_el2, x0
>> msr vmpidr_el2, x1
>> .endm
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 30253bd19917..8ea9c7fdabdb 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -3574,7 +3574,14 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
>> return ((struct sys_reg_desc *)r)->val; \
>> }
>>
>> -FUNCTION_INVARIANT(midr_el1)
>> +static u64 get_midr_el1(struct kvm_vcpu *v, const struct sys_reg_desc *r)
>> +{
>> + ((struct sys_reg_desc *)r)->val = read_sysreg(midr_el1);
>> + if (((struct sys_reg_desc *)r)->val == 0x6D0FD490)
>> + ((struct sys_reg_desc *)r)->val == 0x410FD490;
>> + return ((struct sys_reg_desc *)r)->val;
>> +}
>> +
>> FUNCTION_INVARIANT(revidr_el1)
>> FUNCTION_INVARIANT(aidr_el1)
>>
next prev parent reply other threads:[~2024-02-08 19:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-06 19:58 [RFC PATCH] KVM: arm64: Override Microsoft Azure Cobalt 100 MIDR value with ARM Neoverse N2 Easwar Hariharan
2024-02-07 7:54 ` Anshuman Khandual
2024-02-08 19:16 ` Easwar Hariharan [this message]
2024-02-07 9:49 ` Mark Rutland
2024-02-08 19:16 ` Easwar Hariharan
2024-02-09 11:33 ` Mark Rutland
2024-02-09 18:58 ` Easwar Hariharan
2024-02-07 9:50 ` Marc Zyngier
2024-02-08 19:16 ` Easwar Hariharan
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