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X-CSE-ConnectionGUID: iDiSJ3KrTvir/Ric9QTCyQ== X-CSE-MsgGUID: vSoweTA3RYK7OKecpzB6/g== X-IronPort-AV: E=McAfee;i="6800,10657,11860"; a="86156437" X-IronPort-AV: E=Sophos;i="6.25,196,1779174000"; d="scan'208";a="86156437" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2026 03:51:39 -0700 X-CSE-ConnectionGUID: Z7gsbuS3QT6lTpZGVXkeMA== X-CSE-MsgGUID: ilqusEwTRvqLUdGHKbVmVg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,196,1779174000"; d="scan'208";a="259966933" Received: from dalessan-mobl3.ger.corp.intel.com (HELO [10.245.244.73]) ([10.245.244.73]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2026 03:51:37 -0700 Message-ID: <7f0618ed-d2da-42a1-a605-0660439255d7@linux.intel.com> Date: Fri, 31 Jul 2026 13:51:34 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] usb: xhci: Honor PORTSC.TM if valid To: Konrad Dybcio , Thinh Nguyen , Greg Kroah-Hartman , Mathias Nyman Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, usb4-upstream@oss.qualcomm.com, Raghavendra Thoorpu , Mika Westerberg , Konrad Dybcio References: <20260715-topic-dwc3_tunneling_state-v2-0-026487a08119@oss.qualcomm.com> <20260715-topic-dwc3_tunneling_state-v2-2-026487a08119@oss.qualcomm.com> Content-Language: en-US From: Mathias Nyman In-Reply-To: <20260715-topic-dwc3_tunneling_state-v2-2-026487a08119@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/15/26 15:29, Konrad Dybcio wrote: > From: Konrad Dybcio > > Currently, the only way for the USB core to determine whether the link > is native or tunneled is via an Intel vendor-specific Extended > Capability. > > The XHCI specification v1.2 and newer expose a common ext_cap, > indicating whether BIT(2) of PORTSC can be interpreted as the tunneling > status. > > Make use of that and fall back to the existing Intel-specific path if > the ext_cap is absent. > > Signed-off-by: Konrad Dybcio > --- > drivers/usb/host/xhci-ext-caps.h | 3 +++ > drivers/usb/host/xhci-hub.c | 19 ++++++++++++++++--- > drivers/usb/host/xhci-port.h | 3 ++- > 3 files changed, 21 insertions(+), 4 deletions(-) > > diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h > index 22e53a750e2a..af7d624cd38e 100644 > --- a/drivers/usb/host/xhci-ext-caps.h > +++ b/drivers/usb/host/xhci-ext-caps.h > @@ -66,6 +66,9 @@ > #define XHCI_HLC (1 << 19) > #define XHCI_BLC (1 << 20) > > +/* USB3 tunneling support capability - section 7.11 */ > +#define XHCI_USB3_TUNNELING_SUPPORTED BIT(16) > + > /* Intel SPR shadow capability */ > #define XHCI_INTEL_SPR_ESS_PORT_OFFSET 0x8ac4 /* SuperSpeed port control */ > #define XHCI_INTEL_SPR_TUNEN BIT(4) /* Tunnel mode enabled */ > diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c > index b0264bd8577a..402e98ab95ee 100644 > --- a/drivers/usb/host/xhci-hub.c > +++ b/drivers/usb/host/xhci-hub.c > @@ -766,17 +766,30 @@ static int xhci_exit_test_mode(struct xhci_hcd *xhci) > enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci, > struct xhci_port *port) > { > + void __iomem *base = &xhci->cap_regs->hc_capbase; > struct usb_hcd *hcd; > - void __iomem *base; > u32 offset; > + u32 val; > > - /* Don't try and probe this capability for non-Intel hosts */ > + /* Prefer the XHCI v1.2 ext_cap if advertised */ > + offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_USB3_TUNNELING); > + if (offset) { > + if (!(readl(base + offset) & XHCI_USB3_TUNNELING_SUPPORTED)) > + return USB_LINK_NATIVE; > + The extcap 18 value won't change. We can read it once in xhci_gen_setup()/xhci_setup_port_arrays() and cache it. here we would just check: if (xhci->portsc_tunnel_reporting) { ..read portsc and return, as you do below > + val = xhci_portsc_readl(port); > + if (val & PORT_TM) > + return USB_LINK_TUNNELED; > + > + return USB_LINK_NATIVE; > + } > + Thanks Mathias