From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: William Qiu <william.qiu@starfivetech.com>,
devicetree@vger.kernel.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Linus Walleij <linus.walleij@linaro.org>
Subject: Re: [RESEND v1 2/2] riscv: dts: starfive: Add spi node for JH7110 SoC
Date: Tue, 4 Jul 2023 11:39:29 +0200 [thread overview]
Message-ID: <7f3b600d-d315-22d6-b987-eabfe1b04fdf@linaro.org> (raw)
In-Reply-To: <20230704092200.85401-3-william.qiu@starfivetech.com>
On 04/07/2023 11:22, William Qiu wrote:
> Add spi node for JH7110 SoC.
>
> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Missing SoB.
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 52 ++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 98 +++++++++++++++++++
> 2 files changed, 150 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 2a6d81609284..a066d2e399c4 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -126,6 +126,20 @@ &i2c6 {
> status = "okay";
> };
>
> +&spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins>;
> + status = "okay";
> +
> + spi_dev0: spi@0 {
> + compatible = "st,m25p80";
> + pl022,com-mode = <1>;
> + spi-max-frequency = <10000000>;
> + reg = <0>;
reg is always following compatible, not somewhere deep in properties.
> + status = "okay";
okay is by default
> + };
> +};
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-07-04 9:41 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 9:21 [RESEND v1 0/2] Add SPI module for StarFive JH7110 SoC William Qiu
2023-07-04 9:21 ` [RESEND v1 1/2] dt-binding: spi: constrain minItems of clocks and clock-names William Qiu
2023-07-04 9:38 ` Krzysztof Kozlowski
2023-07-05 3:37 ` William Qiu
2023-07-05 6:00 ` Krzysztof Kozlowski
2023-07-05 6:20 ` William Qiu
2023-07-04 9:22 ` [RESEND v1 2/2] riscv: dts: starfive: Add spi node for JH7110 SoC William Qiu
2023-07-04 9:39 ` Krzysztof Kozlowski [this message]
2023-07-04 12:26 ` Mark Brown
2023-07-04 12:27 ` Krzysztof Kozlowski
2023-07-04 13:16 ` Mark Brown
2023-07-04 13:21 ` Krzysztof Kozlowski
2023-07-04 14:13 ` Mark Brown
2023-07-04 16:41 ` Conor Dooley
2023-07-05 3:40 ` William Qiu
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