From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7243DC54EE9 for ; Tue, 13 Sep 2022 10:52:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231756AbiIMKwT (ORCPT ); Tue, 13 Sep 2022 06:52:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229749AbiIMKwO (ORCPT ); Tue, 13 Sep 2022 06:52:14 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7572A33E1C for ; Tue, 13 Sep 2022 03:52:13 -0700 (PDT) Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4MRgDG5kP3zkWvj; Tue, 13 Sep 2022 18:48:14 +0800 (CST) Received: from kwepemm600007.china.huawei.com (7.193.23.208) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 13 Sep 2022 18:52:11 +0800 Received: from [10.174.185.210] (10.174.185.210) by kwepemm600007.china.huawei.com (7.193.23.208) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 13 Sep 2022 18:52:10 +0800 Subject: Re: A question about Cortex-A73 erratum 858921 To: Marc Zyngier CC: Mark Rutland , Daniel Lezcano , Thomas Gleixner , "wanghaibin.wang@huawei.com" , Zenghui Yu , , References: <87czc4rb1x.wl-maz@kernel.org> From: Kunkun Jiang Message-ID: <7f9bc4fb-67f5-5989-21ba-0833bd3cdd78@huawei.com> Date: Tue, 13 Sep 2022 18:52:09 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <87czc4rb1x.wl-maz@kernel.org> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.174.185.210] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemm600007.china.huawei.com (7.193.23.208) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, Thank you for your reply, I've sent a fix. https://lore.kernel.org/all/20220913104723.332-1-jiangkunkun@huawei.com/ Thanks, Kunkun Jiang On 2022/9/9 20:23, Marc Zyngier wrote: > On Fri, 09 Sep 2022 08:31:43 +0100, > Kunkun Jiang wrote: >> Hi all, >> >> Recently I am learning the code related to Arm arch timer. I found that the >> Cortex-A73 erratum 858921 does not set the corresponding callback functions: >> set_next_event_phys and set_next_event_virt like other erratums. Won't it >> get the wrong value when reading the counter during setting next event? > Yup, you're correct. > > This is a regression introduced by a38b71b0833e > ("clocksource/drivers/arm_arch_timer: Move system register timer > programming over to CVAL"). We used to use the TVAL accessor which > doesn't need a read of the counter, while the switch to CVAL needs > one. Obviously, I didn't enough pay attention to the A73 erratum. > > Please send in a fix for this. > > Thanks, > > M. >