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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f88847506fsm15790665eec.18.2026.05.11.05.16.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 May 2026 05:16:03 -0700 (PDT) Message-ID: <7fcc699e-bf46-4d67-8f66-df1668e2351b@oss.qualcomm.com> Date: Mon, 11 May 2026 20:15:38 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] soc: qcom: ice: Enable PM runtime for ICE driver To: Bjorn Andersson Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Neeraj Soni , Deepti Jaggi References: <20260507112626.2527413-1-linlin.zhang@oss.qualcomm.com> Content-Language: en-US From: Linlin Zhang In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: eYTH7IQlMBbv3oaikfBVXPU4J_LfPo0B X-Proofpoint-GUID: eYTH7IQlMBbv3oaikfBVXPU4J_LfPo0B X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTExMDEzNiBTYWx0ZWRfX/oV0raVOTEWM H8xLQmKzN9P0lKVtLfXR/M6bj7HHbvk9n1utKux5TPL82QJS2giUdwRXGdzMN6ZWgjU5FPC9PwN EofuPEaNdpJpFxfJTT6wQbgfc1OK41pcbInlyWn+cA9+HQmSFqLBGvKEeaQEKU5F6mcdpP4D41F F/3tELyIatpSGXaWd10rYtPir0rESzLzBgqy+ITg3dYltoadNYEB+yHyi3Nd3T8ntZP1d87sRak 4mrMDLgCJ1Djl3ID2C5V2z8xoy6clXdt9xNkdGUZb1Mht6wdLOQV2igi4ZmUsY068xsmpmMSep/ u5VYE4OnPVWYGDk3y+fnzx01xyBqMPtnDVLn1MmnIGE1o8YeSWWqRvcWeGFo/KvKFa52RtlABE8 uUnCRLc7kq/Dq78mIMTNBaD7chlOFrKeW4Pnk3zuYoyzO8FKsbsNY0Ol7CXtJKZBeXr3XP6bE4M Slrt8O2uGSY53vTHB7w== X-Authority-Analysis: v=2.4 cv=SLVykuvH c=1 sm=1 tr=0 ts=6a01c885 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=WYTWnbZezO1wd6nDf14A:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_03,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605110136 On 5/8/2026 5:19 AM, Bjorn Andersson wrote: > On Thu, May 07, 2026 at 04:26:24AM -0700, Linlin Zhang wrote: > > I only got 2 of the 3 patches, and no cover letter. I can see in the > mail headers that you have: > > X-Mailer: git-send-email 2.25.1 > > Use b4 to avoid this kind of mistakes. Thank you for the clarification. I followed an incorrect suggestion to split the original patch series, intending to send different patches to different maintainers. It turns out this was a mistake and resulted in an incomplete series being delivered. The missing cover letter and the other patch are available here: https://lore.kernel.org/all/20260507112454.2527088-1-linlin.zhang@oss.qualcomm.com/ I will resend the full series (cover letter and all patches) together as a single patch set. Sorry for the confusion, and thanks for your patience. > > Regards, > Bjorn > >> The QCOM ICE driver manages the ICE core clock through direct calls to >> clk_prepare_enable() and clk_disable_unprepare(), which limits integration >> with platforms that rely on firmware-managed resources or platform-specific >> power management mechanisms. >> >> Replace direct clock management with runtime PM support by moving clock >> enable and disable into runtime PM callbacks. Use >> pm_runtime_resume_and_get() and pm_runtime_put_sync() in qcom_ice_resume() >> and qcom_ice_suspend() to drive power state transitions, and enable runtime >> PM in qcom_ice_probe(). >> >> Reviewed-by: Neeraj Soni >> Reviewed-by: Deepti Jaggi >> Signed-off-by: Linlin Zhang >> --- >> drivers/soc/qcom/ice.c | 58 ++++++++++++++++++++++++++++++++++++++---- >> 1 file changed, 53 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c >> index b203bc685cad..6f9d679b530c 100644 >> --- a/drivers/soc/qcom/ice.c >> +++ b/drivers/soc/qcom/ice.c >> @@ -16,6 +16,7 @@ >> #include >> #include >> #include >> +#include >> >> #include >> >> @@ -310,8 +311,8 @@ int qcom_ice_resume(struct qcom_ice *ice) >> struct device *dev = ice->dev; >> int err; >> >> - err = clk_prepare_enable(ice->core_clk); >> - if (err) { >> + err = pm_runtime_resume_and_get(dev); >> + if (err < 0) { >> dev_err(dev, "failed to enable core clock (%d)\n", >> err); >> return err; >> @@ -323,7 +324,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); >> >> int qcom_ice_suspend(struct qcom_ice *ice) >> { >> - clk_disable_unprepare(ice->core_clk); >> + pm_runtime_put_sync(ice->dev); >> ice->hwkm_init_complete = false; >> >> return 0; >> @@ -716,24 +717,69 @@ EXPORT_SYMBOL_GPL(devm_of_qcom_ice_get); >> >> static int qcom_ice_probe(struct platform_device *pdev) >> { >> + struct device *dev = &pdev->dev; >> struct qcom_ice *engine; >> void __iomem *base; >> + int ret; >> >> base = devm_platform_ioremap_resource(pdev, 0); >> if (IS_ERR(base)) { >> - dev_warn(&pdev->dev, "ICE registers not found\n"); >> + dev_warn(dev, "ICE registers not found\n"); >> return PTR_ERR(base); >> } >> >> - engine = qcom_ice_create(&pdev->dev, base); >> + engine = qcom_ice_create(dev, base); >> if (IS_ERR(engine)) >> return PTR_ERR(engine); >> >> platform_set_drvdata(pdev, engine); >> >> + ret = devm_pm_runtime_enable(dev); >> + if (ret) { >> + dev_warn(dev, "Enable runtime PM failed, ret: %d\n", ret); >> + return ret; >> + } >> + >> + ret = pm_runtime_resume_and_get(dev); >> + if (ret < 0) { >> + dev_warn(dev, "Runtime PM fails to resume, ret: %d\n", ret); >> + return ret; >> + } >> + >> return 0; >> } >> >> +static void qcom_ice_remove(struct platform_device *pdev) >> +{ >> + pm_runtime_put_sync(&pdev->dev); >> +} >> + >> +static int ice_runtime_resume(struct device *dev) >> +{ >> + struct qcom_ice *ice = dev_get_drvdata(dev); >> + int err = 0; >> + >> + err = clk_prepare_enable(ice->core_clk); >> + if (err) { >> + dev_err(dev, "failed to enable core clock (%d)\n", >> + err); >> + } >> + >> + return err; >> +} >> + >> +static int ice_runtime_suspend(struct device *dev) >> +{ >> + struct qcom_ice *ice = dev_get_drvdata(dev); >> + >> + clk_disable_unprepare(ice->core_clk); >> + return 0; >> +} >> + >> +static const struct dev_pm_ops ice_pm_ops = { >> + SET_RUNTIME_PM_OPS(ice_runtime_suspend, ice_runtime_resume, NULL) >> +}; >> + >> static const struct of_device_id qcom_ice_of_match_table[] = { >> { .compatible = "qcom,inline-crypto-engine" }, >> { }, >> @@ -742,8 +788,10 @@ MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table); >> >> static struct platform_driver qcom_ice_driver = { >> .probe = qcom_ice_probe, >> + .remove = qcom_ice_remove, >> .driver = { >> .name = "qcom-ice", >> + .pm = &ice_pm_ops, >> .of_match_table = qcom_ice_of_match_table, >> }, >> }; >> -- >> 2.34.1 >>