From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932406AbcIMOU2 (ORCPT ); Tue, 13 Sep 2016 10:20:28 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:33955 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758152AbcIMOUA (ORCPT ); Tue, 13 Sep 2016 10:20:00 -0400 From: Kevin Hilman To: jbrunet Cc: Carlo Caione , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family Organization: BayLibre References: <1473409738-27175-1-git-send-email-jbrunet@baylibre.com> <7heg4oq2es.fsf@baylibre.com> <1473753807.2662.12.camel@baylibre.com> Date: Tue, 13 Sep 2016 07:19:53 -0700 In-Reply-To: <1473753807.2662.12.camel@baylibre.com> (jbrunet@baylibre.com's message of "Tue, 13 Sep 2016 10:03:27 +0200") Message-ID: <7h4m5jq3ue.fsf@baylibre.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org jbrunet writes: > On Mon, 2016-09-12 at 13:38 -0700, Kevin Hilman wrote: >> Jerome Brunet writes: >> >> > >> > This patch series adds the necessary pins, clocks and device tree >> > nodes to >> > enable the spifc controller on the GXBB family. I had to add the >> > nand pins >> > in pintctrl as the pinmux setting left by u-boot was conflicting >> > with the >> > spifc pinmux during my test on the P200. >> >> This series seems to be missing a patch which enables the SPIfc on >> the >> P200 board for use with the on-board NOR flash. >> > > Indeed, I did not provide this patch, on purpose. > The SPI-NOR at 4U2 on the P200 schematics was not present on the board > I have. I assumed this was the case for all other P200 as well. > > In addition, to enable the SPI-NOR, you would also need to solder > something at 4R3 (SPI_CS signal disconnected by default) OK, that makes seense. I thought the NOR was on the board by default. > Finally, all the SPIfc lines are shared with the NAND controller which, > like the SPI-NOR, appears on the schematics (4CCN1) but is not soldered > on the actual hardware. > > Of course, I can share such patch for testing purposes if you would > like me to. Yeah, having a testing patch in the list archives would be useful. Thanks, Kevin