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If so, set TI SCI constraint. >> >> TI SCI has a single system-wide latency constraint, so use the max of >> any of the CPU latencies as the system-wide value. >> >> Note: DM firmware clears all constraints at resume time, so >> constraints need to be checked/updated/sent at each system suspend. >> >> Co-developed-by: Vibhore Vardhan >> Signed-off-by: Vibhore Vardhan >> Signed-off-by: Kevin Hilman >> Reviewed-by: Dhruva Gole >> Signed-off-by: Dhruva Gole >> --- >> Depends on the TI SCI series where support for the constraints APIs >> are added: >> https://lore.kernel.org/r/20240801195422.2296347-1-msp@baylibre.com >> > > Unless there is a reason to maintain this patch separately, Could we > add this to the mentioned series -> it is much easier to review and > merge them in one go. Sure, they can be combined for the next version. Kevin