[PATCH 0/2] Add support for clock controllers and CPU scaling for QCS615

[PATCH 0/2] Add support for clock controllers and CPU scaling for QCS615

[Taniya Das]

Add the video, camera, display and gpu clock controller nodes and the
cpufreq-hw node to support cpu scaling.

Clock Dependency:
https://lore.kernel.org/all/20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com/

Device Tree Dependency:
https://lore.kernel.org/all/20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com/

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
Taniya Das (2):
      arm64: dts: qcom: Add clock nodes for multimedia clock
      arm64: dts: qcom: Add cpu scaling clock node

 arch/arm64/boot/dts/qcom/qcs615.dtsi | 80 ++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
---
base-commit: 74741a050b79d31d8d2eeee12c77736596d0a6b2
change-id: 20241108-qcs615-mm-dt-nodes-71ea98a3972a
prerequisite-message-id: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com>
prerequisite-patch-id: 748a4e51bbedae9c6ebdbd642b2fd1badf958788
prerequisite-patch-id: 72a894a3b19fdbd431e1cec9397365bc5b27abfe
prerequisite-patch-id: da2b7a74f1afd58833c6a9a4544a0e271720641f
prerequisite-patch-id: 40b79fe0b9101f5db3bddad23551c1123572aee5
prerequisite-patch-id: cb93e5798f6bfe8cc3044c4ce973e3ae5f20dc6b
prerequisite-patch-id: 13b0dbf97ac1865d241791afb4b46a28ca499523
prerequisite-patch-id: 807019bedabd47c04f7ac78e9461d0b5a6e9131b
prerequisite-patch-id: 8e2e841401fefbd96d78dd4a7c47514058c83bf2
prerequisite-patch-id: 125bb8cb367109ba22cededf6e78754579e1ed03
prerequisite-patch-id: b3cc42570d5826a4704f7702e7b26af9a0fe57b0
prerequisite-patch-id: df8e2fdd997cbf6c0a107f1871ed9e2caaa97582
prerequisite-message-id: <20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com>
prerequisite-patch-id: 09782474af7eecf1013425fd34f9d2f082fb3616
prerequisite-patch-id: 04ca722967256efddc402b7bab94136a5174b0b9
prerequisite-patch-id: 82481c82a20345548e2cb292d3098ed51843b809
prerequisite-patch-id: 3bd8edd83297815fcb1b81fcd891d3c14908442f
prerequisite-patch-id: fc1cfec4ecd56e669c161c4d2c3797fc0abff0ae

Best regards,
-- 
Taniya Das <quic_tdas@quicinc.com>

[PATCH 1/2] arm64: dts: qcom: Add clock nodes for multimedia clock

[Taniya Das]

Add support for video, camera, display and gpu clock controller nodes
for QCS615 platform.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 868808918fd2cdf3f23fcb43ead61b2abfc776f7..8c98ac77dc5c665ef296e65ac76c1b59be485abb 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -3,7 +3,11 @@
  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,qcs615-camcc.h>
+#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
+#include <dt-bindings/clock/qcom,qcs615-videocc.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
@@ -488,6 +492,18 @@ qup_uart0_rx: qup-uart0-rx-state {
 			};
 		};
 
+		gpucc: clock-controller@5090000 {
+			compatible = "qcom,qcs615-gpucc";
+			reg = <0 0x5090000 0 0x9000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GPLL0>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		dc_noc: interconnect@9160000 {
 			reg = <0x0 0x09160000 0x0 0x3200>;
 			compatible = "qcom,qcs615-dc-noc";
@@ -502,6 +518,41 @@ gem_noc: interconnect@9680000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		videocc: clock-controller@ab00000 {
+			compatible = "qcom,qcs615-videocc";
+			reg = <0 0xab00000 0 0x10000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		camcc: clock-controller@ad00000 {
+			compatible = "qcom,qcs615-camcc";
+			reg = <0 0xad00000 0 0x10000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		dispcc: clock-controller@af00000 {
+			compatible = "qcom,qcs615-dispcc";
+			reg = <0 0xaf00000 0 0x20000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,qcs615-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x30000>,

-- 
2.45.2

[PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Taniya Das]

Add cpufreq-hw node to support cpu frequency scaling.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 8c98ac77dc5c665ef296e65ac76c1b59be485abb..2c61da790e78b131e454991c968ece40dd5ca56d 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -33,6 +33,8 @@ cpu0: cpu@0 {
 			power-domains = <&cpu_pd0>;
 			power-domain-names = "psci";
 			next-level-cache = <&l2_0>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;
 
 			l2_0: l2-cache {
@@ -51,6 +53,8 @@ cpu1: cpu@100 {
 			power-domains = <&cpu_pd1>;
 			power-domain-names = "psci";
 			next-level-cache = <&l2_100>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_100: l2-cache {
 			      compatible = "cache";
@@ -68,6 +72,8 @@ cpu2: cpu@200 {
 			power-domains = <&cpu_pd2>;
 			power-domain-names = "psci";
 			next-level-cache = <&l2_200>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_200: l2-cache {
 			      compatible = "cache";
@@ -85,6 +91,8 @@ cpu3: cpu@300 {
 			power-domains = <&cpu_pd3>;
 			power-domain-names = "psci";
 			next-level-cache = <&l2_300>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_300: l2-cache {
 			      compatible = "cache";
@@ -102,6 +110,8 @@ cpu4: cpu@400 {
 			power-domains = <&cpu_pd4>;
 			power-domain-names = "psci";
 			next-level-cache = <&l2_400>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_400: l2-cache {
 			      compatible = "cache";
@@ -119,6 +129,8 @@ cpu5: cpu@500 {
 			power-domains = <&cpu_pd5>;
 			power-domain-names = "psci";
 			next-level-cache = <&l2_500>;
+			clocks = <&cpufreq_hw 0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			l2_500: l2-cache {
 			      compatible = "cache";
@@ -136,6 +148,8 @@ cpu6: cpu@600 {
 			power-domains = <&cpu_pd6>;
 			power-domain-names = "psci";
 			next-level-cache = <&l2_600>;
+			clocks = <&cpufreq_hw 1>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			#cooling-cells = <2>;
 
 			l2_600: l2-cache {
@@ -154,6 +168,8 @@ cpu7: cpu@700 {
 			power-domains = <&cpu_pd7>;
 			power-domain-names = "psci";
 			next-level-cache = <&l2_700>;
+			clocks = <&cpufreq_hw 1>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 
 			l2_700: l2-cache {
 			      compatible = "cache";
@@ -729,6 +745,19 @@ rpmhpd_opp_turbo_l1: opp-9 {
 		};
 	};
 
+	cpufreq_hw: cpufreq@18323000 {
+		compatible = "qcom,cpufreq-hw";
+		reg = <0 0x18323000 0 0x1400>,
+		      <0 0x18325800 0 0x1400>;
+		reg-names = "freq-domain0", "freq-domain1";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+		clock-names = "xo", "alternate";
+
+		#freq-domain-cells = <1>;
+		#clock-cells = <1>;
+	};
+
 	arch_timer: timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

-- 
2.45.2

Re: [PATCH 1/2] arm64: dts: qcom: Add clock nodes for multimedia clock

[Dmitry Baryshkov]

On Fri, Nov 08, 2024 at 11:54:04AM +0530, Taniya Das wrote:
> Add support for video, camera, display and gpu clock controller nodes
> for QCS615 platform.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 868808918fd2cdf3f23fcb43ead61b2abfc776f7..8c98ac77dc5c665ef296e65ac76c1b59be485abb 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -3,7 +3,11 @@
>   * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>  
> +#include <dt-bindings/clock/qcom,qcs615-camcc.h>
> +#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
>  #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> +#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
> +#include <dt-bindings/clock/qcom,qcs615-videocc.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/interconnect/qcom,icc.h>
>  #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
> @@ -488,6 +492,18 @@ qup_uart0_rx: qup-uart0-rx-state {
>  			};
>  		};
>  
> +		gpucc: clock-controller@5090000 {
> +			compatible = "qcom,qcs615-gpucc";
> +			reg = <0 0x5090000 0 0x9000>;

Please pad address field to 8 digits (just the address, not the size)

> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GPLL0>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		dc_noc: interconnect@9160000 {
>  			reg = <0x0 0x09160000 0x0 0x3200>;
>  			compatible = "qcom,qcs615-dc-noc";
> @@ -502,6 +518,41 @@ gem_noc: interconnect@9680000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> +		videocc: clock-controller@ab00000 {
> +			compatible = "qcom,qcs615-videocc";
> +			reg = <0 0xab00000 0 0x10000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&sleep_clk>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		camcc: clock-controller@ad00000 {
> +			compatible = "qcom,qcs615-camcc";
> +			reg = <0 0xad00000 0 0x10000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		dispcc: clock-controller@af00000 {
> +			compatible = "qcom,qcs615-dispcc";
> +			reg = <0 0xaf00000 0 0x20000>;
> +
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		pdc: interrupt-controller@b220000 {
>  			compatible = "qcom,qcs615-pdc", "qcom,pdc";
>  			reg = <0x0 0x0b220000 0x0 0x30000>,
> 
> -- 
> 2.45.2
> 

-- 
With best wishes
Dmitry

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Dmitry Baryshkov]

On Fri, Nov 08, 2024 at 11:54:05AM +0530, Taniya Das wrote:
> Add cpufreq-hw node to support cpu frequency scaling.

CPU, not cpu.
Also the prefix is incorrect for both patches.

> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 8c98ac77dc5c665ef296e65ac76c1b59be485abb..2c61da790e78b131e454991c968ece40dd5ca56d 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -33,6 +33,8 @@ cpu0: cpu@0 {
>  			power-domains = <&cpu_pd0>;
>  			power-domain-names = "psci";
>  			next-level-cache = <&l2_0>;
> +			clocks = <&cpufreq_hw 0>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  			#cooling-cells = <2>;
>  
>  			l2_0: l2-cache {
> @@ -51,6 +53,8 @@ cpu1: cpu@100 {
>  			power-domains = <&cpu_pd1>;
>  			power-domain-names = "psci";
>  			next-level-cache = <&l2_100>;
> +			clocks = <&cpufreq_hw 0>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  
>  			l2_100: l2-cache {
>  			      compatible = "cache";
> @@ -68,6 +72,8 @@ cpu2: cpu@200 {
>  			power-domains = <&cpu_pd2>;
>  			power-domain-names = "psci";
>  			next-level-cache = <&l2_200>;
> +			clocks = <&cpufreq_hw 0>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  
>  			l2_200: l2-cache {
>  			      compatible = "cache";
> @@ -85,6 +91,8 @@ cpu3: cpu@300 {
>  			power-domains = <&cpu_pd3>;
>  			power-domain-names = "psci";
>  			next-level-cache = <&l2_300>;
> +			clocks = <&cpufreq_hw 0>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  
>  			l2_300: l2-cache {
>  			      compatible = "cache";
> @@ -102,6 +110,8 @@ cpu4: cpu@400 {
>  			power-domains = <&cpu_pd4>;
>  			power-domain-names = "psci";
>  			next-level-cache = <&l2_400>;
> +			clocks = <&cpufreq_hw 0>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  
>  			l2_400: l2-cache {
>  			      compatible = "cache";
> @@ -119,6 +129,8 @@ cpu5: cpu@500 {
>  			power-domains = <&cpu_pd5>;
>  			power-domain-names = "psci";
>  			next-level-cache = <&l2_500>;
> +			clocks = <&cpufreq_hw 0>;
> +			qcom,freq-domain = <&cpufreq_hw 0>;
>  
>  			l2_500: l2-cache {
>  			      compatible = "cache";
> @@ -136,6 +148,8 @@ cpu6: cpu@600 {
>  			power-domains = <&cpu_pd6>;
>  			power-domain-names = "psci";
>  			next-level-cache = <&l2_600>;
> +			clocks = <&cpufreq_hw 1>;
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  			#cooling-cells = <2>;
>  
>  			l2_600: l2-cache {
> @@ -154,6 +168,8 @@ cpu7: cpu@700 {
>  			power-domains = <&cpu_pd7>;
>  			power-domain-names = "psci";
>  			next-level-cache = <&l2_700>;
> +			clocks = <&cpufreq_hw 1>;
> +			qcom,freq-domain = <&cpufreq_hw 1>;
>  
>  			l2_700: l2-cache {
>  			      compatible = "cache";
> @@ -729,6 +745,19 @@ rpmhpd_opp_turbo_l1: opp-9 {
>  		};
>  	};
>  
> +	cpufreq_hw: cpufreq@18323000 {
> +		compatible = "qcom,cpufreq-hw";

This doesn't follow the bindings, does it?

> +		reg = <0 0x18323000 0 0x1400>,
> +		      <0 0x18325800 0 0x1400>;
> +		reg-names = "freq-domain0", "freq-domain1";
> +
> +		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> +		clock-names = "xo", "alternate";

Are the DCVSH interrupts?

> +
> +		#freq-domain-cells = <1>;
> +		#clock-cells = <1>;
> +	};
> +
>  	arch_timer: timer {
>  		compatible = "arm,armv8-timer";
>  		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> 
> -- 
> 2.45.2
> 

-- 
With best wishes
Dmitry

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Konrad Dybcio]

On 9.11.2024 1:00 AM, Dmitry Baryshkov wrote:
> On Fri, Nov 08, 2024 at 11:54:05AM +0530, Taniya Das wrote:
>> Add cpufreq-hw node to support cpu frequency scaling.
> 
> CPU, not cpu.
> Also the prefix is incorrect for both patches.
> 
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---

[...]

> 
> This doesn't follow the bindings, does it?
> 
>> +		reg = <0 0x18323000 0 0x1400>,
>> +		      <0 0x18325800 0 0x1400>;
>> +		reg-names = "freq-domain0", "freq-domain1";
>> +
>> +		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>> +		clock-names = "xo", "alternate";
> 
> Are the DCVSH interrupts?

32/33 for silver/gold respectively

Konrad

Re: [PATCH 1/2] arm64: dts: qcom: Add clock nodes for multimedia clock

[Taniya Das]

On 11/9/2024 5:28 AM, Dmitry Baryshkov wrote:
>>   #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
>> @@ -488,6 +492,18 @@ qup_uart0_rx: qup-uart0-rx-state {
>>   			};
>>   		};
>>   
>> +		gpucc: clock-controller@5090000 {
>> +			compatible = "qcom,qcs615-gpucc";
>> +			reg = <0 0x5090000 0 0x9000>;
> Please pad address field to 8 digits (just the address, not the size)
> 

Will fix in the next patch.

>> +

-- 
Thanks & Regards,
Taniya Das.

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Taniya Das]

On 11/9/2024 5:30 AM, Dmitry Baryshkov wrote:
> On Fri, Nov 08, 2024 at 11:54:05AM +0530, Taniya Das wrote:
>> Add cpufreq-hw node to support cpu frequency scaling.
> 
> CPU, not cpu.
> Also the prefix is incorrect for both patches.
> 

Will update to CPU.

>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>>   1 file changed, 29 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 8c98ac77dc5c665ef296e65ac76c1b59be485abb..2c61da790e78b131e454991c968ece40dd5ca56d 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -33,6 +33,8 @@ cpu0: cpu@0 {
>>   			power-domains = <&cpu_pd0>;
>>   			power-domain-names = "psci";
>>   			next-level-cache = <&l2_0>;
>> +			clocks = <&cpufreq_hw 0>;
>> +			qcom,freq-domain = <&cpufreq_hw 0>;
>>   			#cooling-cells = <2>;
>>   
>>   			l2_0: l2-cache {
>> @@ -51,6 +53,8 @@ cpu1: cpu@100 {
>>   			power-domains = <&cpu_pd1>;
>>   			power-domain-names = "psci";
>>   			next-level-cache = <&l2_100>;
>> +			clocks = <&cpufreq_hw 0>;
>> +			qcom,freq-domain = <&cpufreq_hw 0>;
>>   
>>   			l2_100: l2-cache {
>>   			      compatible = "cache";
>> @@ -68,6 +72,8 @@ cpu2: cpu@200 {
>>   			power-domains = <&cpu_pd2>;
>>   			power-domain-names = "psci";
>>   			next-level-cache = <&l2_200>;
>> +			clocks = <&cpufreq_hw 0>;
>> +			qcom,freq-domain = <&cpufreq_hw 0>;
>>   
>>   			l2_200: l2-cache {
>>   			      compatible = "cache";
>> @@ -85,6 +91,8 @@ cpu3: cpu@300 {
>>   			power-domains = <&cpu_pd3>;
>>   			power-domain-names = "psci";
>>   			next-level-cache = <&l2_300>;
>> +			clocks = <&cpufreq_hw 0>;
>> +			qcom,freq-domain = <&cpufreq_hw 0>;
>>   
>>   			l2_300: l2-cache {
>>   			      compatible = "cache";
>> @@ -102,6 +110,8 @@ cpu4: cpu@400 {
>>   			power-domains = <&cpu_pd4>;
>>   			power-domain-names = "psci";
>>   			next-level-cache = <&l2_400>;
>> +			clocks = <&cpufreq_hw 0>;
>> +			qcom,freq-domain = <&cpufreq_hw 0>;
>>   
>>   			l2_400: l2-cache {
>>   			      compatible = "cache";
>> @@ -119,6 +129,8 @@ cpu5: cpu@500 {
>>   			power-domains = <&cpu_pd5>;
>>   			power-domain-names = "psci";
>>   			next-level-cache = <&l2_500>;
>> +			clocks = <&cpufreq_hw 0>;
>> +			qcom,freq-domain = <&cpufreq_hw 0>;
>>   
>>   			l2_500: l2-cache {
>>   			      compatible = "cache";
>> @@ -136,6 +148,8 @@ cpu6: cpu@600 {
>>   			power-domains = <&cpu_pd6>;
>>   			power-domain-names = "psci";
>>   			next-level-cache = <&l2_600>;
>> +			clocks = <&cpufreq_hw 1>;
>> +			qcom,freq-domain = <&cpufreq_hw 1>;
>>   			#cooling-cells = <2>;
>>   
>>   			l2_600: l2-cache {
>> @@ -154,6 +168,8 @@ cpu7: cpu@700 {
>>   			power-domains = <&cpu_pd7>;
>>   			power-domain-names = "psci";
>>   			next-level-cache = <&l2_700>;
>> +			clocks = <&cpufreq_hw 1>;
>> +			qcom,freq-domain = <&cpufreq_hw 1>;
>>   
>>   			l2_700: l2-cache {
>>   			      compatible = "cache";
>> @@ -729,6 +745,19 @@ rpmhpd_opp_turbo_l1: opp-9 {
>>   		};
>>   	};
>>   
>> +	cpufreq_hw: cpufreq@18323000 {
>> +		compatible = "qcom,cpufreq-hw";
> 
> This doesn't follow the bindings, does it?

I will add and re-use the closest target compatible.

> 
>> +		reg = <0 0x18323000 0 0x1400>,
>> +		      <0 0x18325800 0 0x1400>;
>> +		reg-names = "freq-domain0", "freq-domain1";
>> +
>> +		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>> +		clock-names = "xo", "alternate";
> 
> Are the DCVSH interrupts?
> 
This target does not have DCVSH interrupts directly connected to the 
CPUFREQ-HW.

>> +
>> +		#freq-domain-cells = <1>;
>> +		#clock-cells = <1>;
>> +	};
>> +
>>   	arch_timer: timer {
>>   		compatible = "arm,armv8-timer";
>>   		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>>
>> -- 
>> 2.45.2
>>
> 

-- 
Thanks & Regards,
Taniya Das.

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Taniya Das]

On 12/30/2024 10:12 PM, Konrad Dybcio wrote:
> On 9.11.2024 1:00 AM, Dmitry Baryshkov wrote:
>> On Fri, Nov 08, 2024 at 11:54:05AM +0530, Taniya Das wrote:
>>> Add cpufreq-hw node to support cpu frequency scaling.
>>
>> CPU, not cpu.
>> Also the prefix is incorrect for both patches.
>>
>>>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> ---
> 
> [...]
> 
>>
>> This doesn't follow the bindings, does it?
>>
>>> +		reg = <0 0x18323000 0 0x1400>,
>>> +		      <0 0x18325800 0 0x1400>;
>>> +		reg-names = "freq-domain0", "freq-domain1";
>>> +
>>> +		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>>> +		clock-names = "xo", "alternate";
>>
>> Are the DCVSH interrupts?
> 
> 32/33 for silver/gold respectively
> 

This target does not have interrupts connected to CPUFREQ-HW.

> Konrad

-- 
Thanks & Regards,
Taniya Das.

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Dmitry Baryshkov]

On Sun, Jan 19, 2025 at 04:08:20PM +0530, Taniya Das wrote:
> 
> 
> On 11/9/2024 5:30 AM, Dmitry Baryshkov wrote:
> > On Fri, Nov 08, 2024 at 11:54:05AM +0530, Taniya Das wrote:
> > > Add cpufreq-hw node to support cpu frequency scaling.
> > 
> > CPU, not cpu.
> > Also the prefix is incorrect for both patches.
> > 
> 
> Will update to CPU.
> 
> > > 
> > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> > > ---
> > >   arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
> > >   1 file changed, 29 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > index 8c98ac77dc5c665ef296e65ac76c1b59be485abb..2c61da790e78b131e454991c968ece40dd5ca56d 100644
> > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> > > @@ -33,6 +33,8 @@ cpu0: cpu@0 {
> > >   			power-domains = <&cpu_pd0>;
> > >   			power-domain-names = "psci";
> > >   			next-level-cache = <&l2_0>;
> > > +			clocks = <&cpufreq_hw 0>;
> > > +			qcom,freq-domain = <&cpufreq_hw 0>;
> > >   			#cooling-cells = <2>;
> > >   			l2_0: l2-cache {
> > > @@ -51,6 +53,8 @@ cpu1: cpu@100 {
> > >   			power-domains = <&cpu_pd1>;
> > >   			power-domain-names = "psci";
> > >   			next-level-cache = <&l2_100>;
> > > +			clocks = <&cpufreq_hw 0>;
> > > +			qcom,freq-domain = <&cpufreq_hw 0>;
> > >   			l2_100: l2-cache {
> > >   			      compatible = "cache";
> > > @@ -68,6 +72,8 @@ cpu2: cpu@200 {
> > >   			power-domains = <&cpu_pd2>;
> > >   			power-domain-names = "psci";
> > >   			next-level-cache = <&l2_200>;
> > > +			clocks = <&cpufreq_hw 0>;
> > > +			qcom,freq-domain = <&cpufreq_hw 0>;
> > >   			l2_200: l2-cache {
> > >   			      compatible = "cache";
> > > @@ -85,6 +91,8 @@ cpu3: cpu@300 {
> > >   			power-domains = <&cpu_pd3>;
> > >   			power-domain-names = "psci";
> > >   			next-level-cache = <&l2_300>;
> > > +			clocks = <&cpufreq_hw 0>;
> > > +			qcom,freq-domain = <&cpufreq_hw 0>;
> > >   			l2_300: l2-cache {
> > >   			      compatible = "cache";
> > > @@ -102,6 +110,8 @@ cpu4: cpu@400 {
> > >   			power-domains = <&cpu_pd4>;
> > >   			power-domain-names = "psci";
> > >   			next-level-cache = <&l2_400>;
> > > +			clocks = <&cpufreq_hw 0>;
> > > +			qcom,freq-domain = <&cpufreq_hw 0>;
> > >   			l2_400: l2-cache {
> > >   			      compatible = "cache";
> > > @@ -119,6 +129,8 @@ cpu5: cpu@500 {
> > >   			power-domains = <&cpu_pd5>;
> > >   			power-domain-names = "psci";
> > >   			next-level-cache = <&l2_500>;
> > > +			clocks = <&cpufreq_hw 0>;
> > > +			qcom,freq-domain = <&cpufreq_hw 0>;
> > >   			l2_500: l2-cache {
> > >   			      compatible = "cache";
> > > @@ -136,6 +148,8 @@ cpu6: cpu@600 {
> > >   			power-domains = <&cpu_pd6>;
> > >   			power-domain-names = "psci";
> > >   			next-level-cache = <&l2_600>;
> > > +			clocks = <&cpufreq_hw 1>;
> > > +			qcom,freq-domain = <&cpufreq_hw 1>;
> > >   			#cooling-cells = <2>;
> > >   			l2_600: l2-cache {
> > > @@ -154,6 +168,8 @@ cpu7: cpu@700 {
> > >   			power-domains = <&cpu_pd7>;
> > >   			power-domain-names = "psci";
> > >   			next-level-cache = <&l2_700>;
> > > +			clocks = <&cpufreq_hw 1>;
> > > +			qcom,freq-domain = <&cpufreq_hw 1>;
> > >   			l2_700: l2-cache {
> > >   			      compatible = "cache";
> > > @@ -729,6 +745,19 @@ rpmhpd_opp_turbo_l1: opp-9 {
> > >   		};
> > >   	};
> > > +	cpufreq_hw: cpufreq@18323000 {
> > > +		compatible = "qcom,cpufreq-hw";
> > 
> > This doesn't follow the bindings, does it?
> 
> I will add and re-use the closest target compatible.
> 
> > 
> > > +		reg = <0 0x18323000 0 0x1400>,
> > > +		      <0 0x18325800 0 0x1400>;
> > > +		reg-names = "freq-domain0", "freq-domain1";
> > > +
> > > +		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> > > +		clock-names = "xo", "alternate";
> > 
> > Are the DCVSH interrupts?
> > 
> This target does not have DCVSH interrupts directly connected to the
> CPUFREQ-HW.

So, does it require a separate LMH driver, like the one used for sdm845?

> 
> > > +
> > > +		#freq-domain-cells = <1>;
> > > +		#clock-cells = <1>;
> > > +	};
> > > +
> > >   	arch_timer: timer {
> > >   		compatible = "arm,armv8-timer";
> > >   		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > > 
> > > -- 
> > > 2.45.2
> > > 
> > 
> 
> -- 
> Thanks & Regards,
> Taniya Das.
> 

-- 
With best wishes
Dmitry

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Taniya Das]

On 1/20/2025 2:16 PM, Dmitry Baryshkov wrote:
>>> This doesn't follow the bindings, does it?
>> I will add and re-use the closest target compatible.
>>
>>>> +		reg = <0 0x18323000 0 0x1400>,
>>>> +		      <0 0x18325800 0 0x1400>;
>>>> +		reg-names = "freq-domain0", "freq-domain1";
>>>> +
>>>> +		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>>>> +		clock-names = "xo", "alternate";
>>> Are the DCVSH interrupts?
>>>
>> This target does not have DCVSH interrupts directly connected to the
>> CPUFREQ-HW.
> So, does it require a separate LMH driver, like the one used for sdm845?

I will check how it is handled on QCS615 as it is closer to SC7180 and I 
didn't see any LMH handling there as well.

-- 
Thanks & Regards,
Taniya Das.

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Dmitry Baryshkov]

On Mon, 20 Jan 2025 at 12:34, Taniya Das <quic_tdas@quicinc.com> wrote:
>
>
>
> On 1/20/2025 2:16 PM, Dmitry Baryshkov wrote:
> >>> This doesn't follow the bindings, does it?
> >> I will add and re-use the closest target compatible.
> >>
> >>>> +          reg = <0 0x18323000 0 0x1400>,
> >>>> +                <0 0x18325800 0 0x1400>;
> >>>> +          reg-names = "freq-domain0", "freq-domain1";
> >>>> +
> >>>> +          clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> >>>> +          clock-names = "xo", "alternate";
> >>> Are the DCVSH interrupts?
> >>>
> >> This target does not have DCVSH interrupts directly connected to the
> >> CPUFREQ-HW.
> > So, does it require a separate LMH driver, like the one used for sdm845?
>
> I will check how it is handled on QCS615 as it is closer to SC7180 and I
> didn't see any LMH handling there as well.

At least sm6150-thermal.dtsi declares two LMH blocks.


-- 
With best wishes
Dmitry

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Taniya Das]

On 1/20/2025 4:06 PM, Dmitry Baryshkov wrote:
> On Mon, 20 Jan 2025 at 12:34, Taniya Das <quic_tdas@quicinc.com> wrote:
>>
>>
>>
>> On 1/20/2025 2:16 PM, Dmitry Baryshkov wrote:
>>>>> This doesn't follow the bindings, does it?
>>>> I will add and re-use the closest target compatible.
>>>>
>>>>>> +          reg = <0 0x18323000 0 0x1400>,
>>>>>> +                <0 0x18325800 0 0x1400>;
>>>>>> +          reg-names = "freq-domain0", "freq-domain1";
>>>>>> +
>>>>>> +          clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>>>>>> +          clock-names = "xo", "alternate";
>>>>> Are the DCVSH interrupts?
>>>>>
>>>> This target does not have DCVSH interrupts directly connected to the
>>>> CPUFREQ-HW.
>>> So, does it require a separate LMH driver, like the one used for sdm845?
>>
>> I will check how it is handled on QCS615 as it is closer to SC7180 and I
>> didn't see any LMH handling there as well.
> 
> At least sm6150-thermal.dtsi declares two LMH blocks.

QCS615 also has 2 LMH blocks, but the handling of interrupts will be 
done from the LMH driver, integration with CPUFREQ-HW driver is still 
under evaluation.

-- 
Thanks & Regards,
Taniya Das.

Re: [PATCH 2/2] arm64: dts: qcom: Add cpu scaling clock node

[Konrad Dybcio]

On 20.01.2025 11:57 AM, Taniya Das wrote:
> 
> 
> On 1/20/2025 4:06 PM, Dmitry Baryshkov wrote:
>> On Mon, 20 Jan 2025 at 12:34, Taniya Das <quic_tdas@quicinc.com> wrote:
>>>
>>>
>>>
>>> On 1/20/2025 2:16 PM, Dmitry Baryshkov wrote:
>>>>>> This doesn't follow the bindings, does it?
>>>>> I will add and re-use the closest target compatible.
>>>>>
>>>>>>> +          reg = <0 0x18323000 0 0x1400>,
>>>>>>> +                <0 0x18325800 0 0x1400>;
>>>>>>> +          reg-names = "freq-domain0", "freq-domain1";
>>>>>>> +
>>>>>>> +          clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>>>>>>> +          clock-names = "xo", "alternate";
>>>>>> Are the DCVSH interrupts?
>>>>>>
>>>>> This target does not have DCVSH interrupts directly connected to the
>>>>> CPUFREQ-HW.
>>>> So, does it require a separate LMH driver, like the one used for sdm845?
>>>
>>> I will check how it is handled on QCS615 as it is closer to SC7180 and I
>>> didn't see any LMH handling there as well.
>>
>> At least sm6150-thermal.dtsi declares two LMH blocks.
> 
> QCS615 also has 2 LMH blocks, but the handling of interrupts will be done from the LMH driver, integration with CPUFREQ-HW driver is still under evaluation.

Currently platforms from the 8150 era, using drivers/thermal/qcom/lmh.c
expose the LMH device as an irqchip and pass the per-instance IRQ it
provides to cpufreq, instead of the latter directly consuming a GIC irq

Konrad