From: Bart Van Assche <bvanassche@acm.org>
To: Anjana Hari <quic_ahari@quicinc.com>,
agross@kernel.org, andersson@kernel.org, jejb@linux.ibm.com,
martin.petersen@oracle.com
Cc: alim.akhtar@samsung.com, avri.altman@wdc.com,
konrad.dybcio@linaro.org, linux-scsi@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_narepall@quicinc.com,
quic_nitirawa@quicinc.com, quic_rampraka@quicinc.com
Subject: Re: [PATCH 1/2] scsi: ufs: core: Add hibernation callbacks
Date: Thu, 29 Dec 2022 07:06:38 -0800 [thread overview]
Message-ID: <82272e6d-e175-ad46-e66b-7eb5e51964c3@acm.org> (raw)
In-Reply-To: <20221221171222.19699-2-quic_ahari@quicinc.com>
On 12/21/22 09:12, Anjana Hari wrote:
> Add hibernation call backs - freeze, restore and thaw.
> Add the respective prototypes.
>
> Signed-off-by: Anjana Hari <quic_ahari@quicinc.com>
> ---
> drivers/ufs/core/ufshcd.c | 80 +++++++++++++++++++++++++++++++++++++++
> include/ufs/ufshcd.h | 6 +++
> 2 files changed, 86 insertions(+)
>
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index bda61be5f035..c216a97dc1dd 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -9453,6 +9453,25 @@ static int ufshcd_resume(struct ufs_hba *hba)
>
> /* enable the host irq as host controller would be active soon */
> ufshcd_enable_irq(hba);
> +
> + if (hba->restore) {
> + /* Configure UTRL and UTMRL base address registers */
> + ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
> + REG_UTP_TRANSFER_REQ_LIST_BASE_L);
> + ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
> + REG_UTP_TRANSFER_REQ_LIST_BASE_H);
> + ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
> + REG_UTP_TASK_REQ_LIST_BASE_L);
> + ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
> + REG_UTP_TASK_REQ_LIST_BASE_H);
> + /* Commit the registers */
> + mb();
> + }
The comment above the mb() call is wrong. No matter the type of a
barrier, a barrier controls the order in which load, store and/or MMIO
operations happen. A barrier does not "commit" register writes.
The comment above mb() should explain which load, store and/or MMIO
accesses are ordered and also why the ordering is necessary.
> + /*
> + * Ensure no runtime PM operations take
> + * place in the hibernation and restore sequence
> + * on successful freeze operation.
> + */
> + if (!ret)
> + pm_runtime_disable(hba->dev);
I think the power management core already serializes system-wide power
management state transitions and runtime power management and hence that
the above code can be left out.
> + /*
> + * Now any runtime PM operations can be
> + * allowed on successful restore operation
> + */
> + if (!ret)
> + pm_runtime_enable(hba->dev);
Same comment for the above code.
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(ufshcd_system_restore);
> +
> +int ufshcd_system_thaw(struct device *dev)
> +{
> +
> + struct ufs_hba *hba = dev_get_drvdata(dev);
> + int ret = 0;
> +
> + ret = ufshcd_system_resume(dev);
> + if (!ret)
> + pm_runtime_enable(hba->dev);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(ufshcd_system_thaw);
Also here, please remove the code related to runtime power management.
> diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
> index 5cf81dff60aa..dadb3c732be4 100644
> --- a/include/ufs/ufshcd.h
> +++ b/include/ufs/ufshcd.h
> @@ -978,6 +978,9 @@ struct ufs_hba {
> #endif
> u32 luns_avail;
> bool complete_put;
> +
> + /* Distinguish between resume and restore */
> + bool restore;
> };
Please convert this member variable into a function argument. This
probably will require adding an argument to existing functions.
Thanks,
Bart.
next prev parent reply other threads:[~2022-12-29 15:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-21 17:12 [PATCH 0/2] scsi: ufs: Add hibernation callbacks Anjana Hari
2022-12-21 17:12 ` [PATCH 1/2] scsi: ufs: core: " Anjana Hari
2022-12-21 19:01 ` kernel test robot
2022-12-22 7:01 ` kernel test robot
2022-12-22 7:01 ` kernel test robot
2022-12-29 15:06 ` Bart Van Assche [this message]
2022-12-21 17:12 ` [PATCH 2/2] scsi: ufs: ufs-qcom: " Anjana Hari
2022-12-27 21:31 ` kernel test robot
2022-12-29 20:59 ` kernel test robot
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