From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C3A3D28F5 for ; Wed, 1 Jul 2026 10:11:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782900701; cv=none; b=SngYjkEbtRzylWvmZdFLN5OVnLoPyxlPMFFktG3M604GJlVDqzZub0u3GvCSVvZLozG0zRKqBZroRHvjVk/IY6FzLT2r1gOwajSwhUs2CvEv49s4GbPMG2kMU/XH9nVtCG7ehZ0FBIfiT1fFwOXTbtBBkQnVSXCInnaJH0i2eHY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782900701; c=relaxed/simple; bh=GCujk2R5vMwTbm59tbrnwfcbiLxK4IZAXVxai7uFQuI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=SHt1cEPvRKfpJBYL/gAX9bCijG52qUVegjwzyfBMYacIho99TPB2memWlmWW3VVwqAnOa6fNOAtHFsMdKavyC09jN4pUObyg22UljKzEghz8fSJXYgv1rZlTbMDZT6KW6xmKkvNhAuizUu40sm9/juNpCnzax0VHbvAQaS+59Bw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=f08AZdiB; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="f08AZdiB" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7AA322BCC; Wed, 1 Jul 2026 03:11:34 -0700 (PDT) Received: from [10.57.30.25] (unknown [10.57.30.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7624B3F85F; Wed, 1 Jul 2026 03:11:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1782900698; bh=GCujk2R5vMwTbm59tbrnwfcbiLxK4IZAXVxai7uFQuI=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=f08AZdiB7CEFN8nAGQMT/lCGlFQgIL5I0j38ruBq3e6ISOnGNa6twAUC20um9R67K O6F594EIh9yieP+/2Rl61cdQ3wCf3pKrAJJGlxbMODAYFVXNVT3ydcDh/hBs1BFMfN K5AeIZ+8sQ/F5mkbHCfL/rBMbPIIVySOLQLmu6Eo= Message-ID: <830a4d39-c829-4e79-a0ec-5a3633b58aa6@arm.com> Date: Wed, 1 Jul 2026 11:11:35 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] Add BBML3 cpu feature Content-Language: en-GB To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260701094131.677636-1-linu.cherian@arm.com> From: Suzuki K Poulose In-Reply-To: <20260701094131.677636-1-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 01/07/2026 10:41, Linu Cherian wrote: > Patches 1 and 2 introduces BBML3 cpu feature > Patches 3, 4 and 5 adds more cpus to the BBML3 support list, > which dont advertise themselves through the standard > MMFR2_ID registers. > > Linu Cherian (5): > arm64: cpufeature: Add BBML3 > arm64: cpufeature: Detect BBML3 based on MMFR2 ID > arm64: cputype: Add Cortex-A520AE definitions > arm64: cputype: Add C1-Nano definitions > arm64: cpufeature: Extend bbml3 support list If you could move the last 3 patches to the top, would be easier for people to back port the "enable" BBLM3 for those CPUs, without the renaming conflicts. Suzuki > > arch/arm64/include/asm/cpufeature.h | 6 ++-- > arch/arm64/include/asm/cputype.h | 4 +++ > arch/arm64/kernel/cpufeature.c | 51 +++++++++++++--------------- > arch/arm64/mm/contpte.c | 21 +++++------- > arch/arm64/mm/mmu.c | 52 ++++++++++++++--------------- > arch/arm64/mm/proc.S | 4 +-- > arch/arm64/tools/cpucaps | 2 +- > arch/arm64/tools/sysreg | 1 + > 8 files changed, 69 insertions(+), 72 deletions(-) >