Re: [PATCH 1/1] PCI: dwc: Apply ECRC workaround for DesignWare cores prior to 5.10A

[Jon Hunter <jonathanh@nvidia.com>]

On 10/04/2026 07:25, Manikanta Maddireddy wrote:
> The ECRC (TLP digest) workaround was originally applied only for DesignWare
> core version 4.90a. Per discussion in Synopsys case, the dependency of the
> iATU TD bit on ECRC generation was removed in 5.10a, so apply the
> workaround for all DWC versions below that release.
> 
> Replace the misleading comment that referred to raw version constants
> with readable DesignWare release name aligned with the implementation.
> 
> Fixes: b210b1595606 PCI: dwc: Apply ECRC workaround to DesignWare 5.00a as well
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/controller/dwc/pcie-designware.c | 6 +++---
>   drivers/pci/controller/dwc/pcie-designware.h | 1 +
>   2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index d69db0ab3b14..d0b3b93fc940 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -487,8 +487,8 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg
>   static inline u32 dw_pcie_enable_ecrc(u32 val)
>   {
>   	/*
> -	 * DWC versions 0x3530302a and 0x3536322a has a design issue where the 'TD'
> -	 * bit in the Control register-1 of the ATU outbound region acts
> +	 * DesignWare core versions prior to 5.10A have a design issue where the
> +	 * 'TD' bit in the Control register-1 of the ATU outbound region acts
>   	 * like an override for the ECRC setting, i.e., the presence of TLP
>   	 * Digest (ECRC) in the outgoing TLPs is solely determined by this
>   	 * bit. This is contrary to the PCIe spec which says that the
> @@ -563,7 +563,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
>   	if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) &&
>   	    dw_pcie_ver_is_ge(pci, 460A))
>   		val |= PCIE_ATU_INCREASE_REGION_SIZE;
> -	if (dw_pcie_ver_is(pci, 490A) || dw_pcie_ver_is(pci, 500A))
> +	if (!dw_pcie_ver_is_ge(pci, 510A))
>   		val = dw_pcie_enable_ecrc(val);
>   	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
>   
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 82946bf78b21..739a213c27c9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -35,6 +35,7 @@
>   #define DW_PCIE_VER_480A		0x3438302a
>   #define DW_PCIE_VER_490A		0x3439302a
>   #define DW_PCIE_VER_500A		0x3530302a
> +#define DW_PCIE_VER_510A		0x3531302a
>   #define DW_PCIE_VER_520A		0x3532302a
>   #define DW_PCIE_VER_540A		0x3534302a
>   #define DW_PCIE_VER_562A		0x3536322a


Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Thanks!
Jon

-- 
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