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From: Abhishek Sahu <absahu@codeaurora.org>
To: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Archit Taneja <architt@codeaurora.org>,
	dwmw2@infradead.org, computersforpeace@gmail.com,
	marek.vasut@gmail.com, richard@nod.at,
	cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,
	mark.rutland@arm.com, devicetree@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mtd@lists.infradead.org, andy.gross@linaro.org,
	sricharan@codeaurora.org
Subject: Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA
Date: Mon, 17 Jul 2017 14:19:47 +0530	[thread overview]
Message-ID: <840a0ceca8892fb343fc617322aad3ba@codeaurora.org> (raw)
In-Reply-To: <20170717092234.001fb765@bbrezillon>

On 2017-07-17 12:52, Boris Brezillon wrote:
> On Mon, 17 Jul 2017 11:41:01 +0530
> Abhishek Sahu <absahu@codeaurora.org> wrote:
> 
>> >> > +
>> >> > +nand@79b0000 {
>> >
>> > nand-controller@xxxx {
>> >
>> > BTW, glad to see another driver moving to the new DT representation
>> > :-).
>> >
>> >> > +	compatible = "qcom,qpic-nandc-v1.4.0";
>> >> > +	reg = <0x79b0000 0x1000>;
>> >> > +
>> >> > +	clocks = <&gcc GCC_QPIC_CLK>,
>> >> > +		<&gcc GCC_QPIC_AHB_CLK>;
>> >> > +	clock-names = "core", "aon";
>> >> > +
>> >> > +	#address-cells = <1>;
>> >> > +	#size-cells = <0>;
>> >> > +
>> >> > +	nandcs@0 {
>> >
>> > 	nand@0 {
>> >
>> >> > +		compatible = "qcom,nandcs";
>> >
>> > Why do you need a compatible here?
>> It is the part of original driver. We can connect multiple
>> NAND devices in the same bus and qcom,nandcs is being used
>> for each connected NAND device. Each NAND device can use
>> different  chip select, ecc strength etc which we can specify
>> under this sub node.
> 
> 
> Still don't understand why you need a compatible? Is this a memory bus
> where you can connect other kind of memories (parallel NORs,
> SRAMs, ...)?
> 
> If that's not the case, then considering all subnodes of the
> nand-controller node containing a reg property as NAND devices is fine,
> you don't need this compatible = "nand,cs" (see sunxi-nand bindings
> [1]).
> 

  Thanks Boris for giving detailed references.

  We can connect other parallel devices also but we have
  different hardware wrappers over generic EBI2/QPIC which
  will MUX/arbitrate the device access from the hardware itself.
  So this NAND driver will only control multiple NAND devices.

  We can remove this compatible and use the bindings
  similar to sunxi-nand. I will do the required changes and
  will post in v2 of the same patch series.

> If the bus is generic and can be attached non-NAND devices, I'd
> recommend looking at atmel's binding [2], because you're likely to
> have one instance of the NAND controller logic for all NAND devices
> connected on this bus.
> And more importantly, if the bus a generic, the node should not be
> named nand or nand-controller, and the compatible should not contain
> 'nandc' in it.
> 
> [1]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt#L34
> [2]http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mtd/atmel-nand.txt#L70

-- 
Abhishek Sahu

  reply	other threads:[~2017-07-17  8:49 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-29  7:15 [PATCH 00/14] Add QCOM QPIC NAND support Abhishek Sahu
2017-06-29  7:15 ` [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA Abhishek Sahu
2017-06-29  9:46   ` Marek Vasut
2017-07-03  4:38   ` Archit Taneja
2017-07-03 19:41     ` Boris Brezillon
2017-07-17  6:11       ` Abhishek Sahu
2017-07-17  7:22         ` Boris Brezillon
2017-07-17  8:49           ` Abhishek Sahu [this message]
2017-07-03  6:21   ` Sricharan R
2017-06-29  7:15 ` [PATCH 02/14] qcom: mtd: nand: add and initialize QPIC DMA resources Abhishek Sahu
2017-06-29  9:48   ` Marek Vasut
2017-07-17  6:36     ` Abhishek Sahu
2017-07-03  5:17   ` Archit Taneja
2017-07-17  6:26     ` Abhishek Sahu
2017-07-03  6:24   ` Sricharan R
2017-07-03  6:32   ` Sricharan R
2017-06-29  7:15 ` [PATCH 03/14] qcom: mtd: nand: Fixed config error for BCH Abhishek Sahu
2017-06-29  9:49   ` Marek Vasut
2017-07-03 19:47     ` Boris Brezillon
2017-07-17  6:38       ` Abhishek Sahu
2017-07-03  6:25   ` Sricharan R
2017-06-29  7:15 ` [PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing Abhishek Sahu
2017-06-29  7:15 ` [PATCH 05/14] qcom: mtd: nand: allocate bam transaction Abhishek Sahu
2017-06-29  9:50   ` Marek Vasut
2017-07-17  6:42     ` Abhishek Sahu
2017-07-03  8:22   ` Sricharan R
2017-07-17  6:44     ` Abhishek Sahu
2017-06-29  7:15 ` [PATCH 06/14] qcom: mtd: nand: add bam dma descriptor handling Abhishek Sahu
2017-07-04  6:10   ` Archit Taneja
2017-07-17  6:47     ` Abhishek Sahu
2017-06-29  7:15 ` [PATCH 07/14] qcom: mtd: nand: support for passing flags in transfer functions Abhishek Sahu
2017-06-29  9:52   ` Marek Vasut
2017-07-04  6:49   ` Archit Taneja
2017-07-10 14:10     ` Sricharan R
2017-07-17  6:59       ` Abhishek Sahu
2017-06-29  7:16 ` [PATCH 08/14] qcom: mtd: nand: Add support for additional CSRs Abhishek Sahu
2017-07-04  6:54   ` Archit Taneja
2017-07-17  7:10     ` Abhishek Sahu
2017-06-29  7:16 ` [PATCH 09/14] qcom: mtd: nand: BAM support for read page Abhishek Sahu
2017-07-04  9:40   ` Archit Taneja
2017-07-10 14:15     ` Sricharan R
2017-07-17  7:17     ` Abhishek Sahu
2017-06-29  7:16 ` [PATCH 10/14] qcom: mtd: nand: support for QPIC Page read/write Abhishek Sahu
2017-07-04  9:44   ` Archit Taneja
2017-07-17  7:25     ` Abhishek Sahu
2017-07-10 14:18   ` Sricharan R
2017-07-17  7:36     ` Abhishek Sahu
2017-06-29  7:16 ` [PATCH 11/14] qcom: mtd: nand: BAM raw read and write support Abhishek Sahu
2017-06-29  7:16 ` [PATCH 12/14] qcom: mtd: nand: change register offset defines with enums Abhishek Sahu
2017-07-04  9:55   ` Archit Taneja
2017-07-17  7:31     ` Abhishek Sahu
2017-06-29  7:16 ` [PATCH 13/14] qcom: mtd: nand: support for QPIC version 1.5.0 Abhishek Sahu
2017-07-04  9:57   ` Archit Taneja
2017-07-17  7:32     ` Abhishek Sahu
2017-06-29  7:16 ` [PATCH 14/14] qcom: mtd: nand: programmed NAND_DEV_CMD_VLD register Abhishek Sahu

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