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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.3 (3.54.3-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Fri, 2025-06-06 at 01:45 +0300, Nadav Amit wrote: >=20 > However, I think perhaps the bigger issue is that you want to assume > all cores have the same RAR settings, and right now it might be a bit > inconsistent. The documentation strongly suggests that RAR_INFO.TableMaxIndex is architecturally determined, and always 64 on Sapphire Rapids. I'm not sure we want code to handle a case the Intel documentation seems to suggest cannot exist. Maybe somebody from Intel has some firmer ideas here? >=20 > So you may want to do some initial checks on the BSP as for > whether RAR is supported and what rar_max_payloads is (e.g., in > bsp_init_intel() ). And then on each AP, in something like=20 > init_intel() you=E2=80=99d call setup_clear_cpu_cap() to disable RAR if a= ny > CPU's max_payloads is different than the BSP. Grabbing the value of rar_max_payloads from early_init_intel() might make sense, since it is supposed to be a system-wide value, and not a per CPU thing. That seems like it would solve data race issues? >=20 > [ BTW: further regarding patch 4, it seems cleaner to call > =C2=A0 rar_cpu_init() from Intel specific code like init_intel() ? ] >=20 Good idea, I'll move the call there. > Just sharing my thoughts (and further clarifying them), >=20 I appreciate the comments and suggestions! Now that the code seems to (finally) work reliably, I should have a faster turnaround time incorporating people's suggestions, too. --=20 All Rights Reversed.