Re: [PATCH v2 2/4] iommu/vt-d: Set PGSNP bit in pasid table entry for SVA binding

[Lu Baolu <baolu.lu@linux.intel.com>]

On 2022/4/22 11:05, Tian, Kevin wrote:
>> From: Lu Baolu <baolu.lu@linux.intel.com>
>> Sent: Thursday, April 21, 2022 7:36 PM
>>
>> This field make the requests snoop processor caches irrespective of
>> other attributes in the request or other fields in paging structure
>> entries used to translate the request.
> 
> I think you want to first point out the fact that SVA wants snoop
> cache instead of just talking about the effect of PGSNP.
> 
> But thinking more I wonder why PGSNP is ever required. This is
> similar to DMA API case. x86 is already cache coherent for normal
> DMA (if not setting PCI no-snoop) and if the driver knows no-snoop
> is incompatible to SVA API then it should avoid triggering no-snoop
> traffic for SVA usage. In this case it is pointless for IOMMU driver
> to enable force-snooping. Even in the future certain platform allows
> no-snoop usage w/ SVA (I'm not sure how it works) this again should
> be reflected by additional SVA APIs for driver to explicitly manage.
> 
> force-snoop should be enabled only in device assignment case IMHO,
> orthogonal to whether vSVA is actually used.
> 
> Did I misunderstand the motivation here?

No, you didn't.

Let's talk with the arch guys for more details before move this patch
ahead. Thanks for pointing this out.

Best regards,
baolu

> 
>>
>> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
>> ---
>>   drivers/iommu/intel/svm.c | 9 ++++++---
>>   1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c
>> index 23a38763c1d1..c720d1be992d 100644
>> --- a/drivers/iommu/intel/svm.c
>> +++ b/drivers/iommu/intel/svm.c
>> @@ -391,9 +391,12 @@ static struct iommu_sva
>> *intel_svm_bind_mm(struct intel_iommu *iommu,
>>   	}
>>
>>   	/* Setup the pasid table: */
>> -	sflags = (flags & SVM_FLAG_SUPERVISOR_MODE) ?
>> -			PASID_FLAG_SUPERVISOR_MODE : 0;
>> -	sflags |= cpu_feature_enabled(X86_FEATURE_LA57) ?
>> PASID_FLAG_FL5LP : 0;
>> +	sflags = PASID_FLAG_PAGE_SNOOP;
>> +	if (flags & SVM_FLAG_SUPERVISOR_MODE)
>> +		sflags |= PASID_FLAG_SUPERVISOR_MODE;
>> +	if (cpu_feature_enabled(X86_FEATURE_LA57))
>> +		sflags |= PASID_FLAG_FL5LP;
>> +
>>   	spin_lock_irqsave(&iommu->lock, iflags);
>>   	ret = intel_pasid_setup_first_level(iommu, dev, mm->pgd, mm-
>>> pasid,
>>   					    FLPT_DEFAULT_DID, sflags);
>> --
>> 2.25.1
>