From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 325FEC433EF for ; Tue, 26 Jul 2022 09:49:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238508AbiGZJtE (ORCPT ); Tue, 26 Jul 2022 05:49:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232651AbiGZJtC (ORCPT ); Tue, 26 Jul 2022 05:49:02 -0400 Received: from extserv.mm-sol.com (ns.mm-sol.com [37.157.136.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BC2B31362; Tue, 26 Jul 2022 02:49:01 -0700 (PDT) Received: from [192.168.1.5] (unknown [195.24.90.54]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client did not present a certificate) (Authenticated sender: svarbanov@mm-sol.com) by extserv.mm-sol.com (Postfix) with ESMTPSA id 6D45ACF07; Tue, 26 Jul 2022 12:48:57 +0300 (EEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mm-sol.com; s=201706; t=1658828938; bh=kuP/AqMl37flBhHYfa+ehxb0nM3e+R5DB7qOmDEcunI=; h=Date:Subject:To:Cc:From:From; b=BFgHQihVipwWP6uJcORqzD/XiviB2hku6DOW5Ns8NQDGdwiHcW0+N8sfE4hfhpYbK 7lkp4t9oNu0TZO9J+9DZoHFhE9feRmEjTbWfQSCyTPzI3toqtKCyi/HFOD2W2gS5K9 Psk6WrkGalcYH9apfcGKPTad115AKiXIy8M1O+pbyUkfUic0cMjlaCGwoLgIYV9r7J NxZkoHSfSotuLom9Dg0PA5uuarb3uvxvBr+2vFoEvT9t5r9PHw3eOKk0ei//TxQ0v1 I74mYx6DoigmljKLlc5+Me4+dexISvmrrQiLx1anHn7Pw3B8nuiahDGoaVOCaDXCE2 FewLV0K4kC6lg== Message-ID: <8472601e-9ea4-1ebe-dfd9-c193764d1a04@mm-sol.com> Date: Tue, 26 Jul 2022 12:48:54 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v3] PCI: qcom: Allow L1 and its sub states Content-Language: en-US To: Krishna chaitanya chundru , helgaas@kernel.org Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, Andy Gross , Bjorn Andersson , Lorenzo Pieralisi , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas References: <1657886366-32685-1-git-send-email-quic_krichai@quicinc.com> From: Stanimir Varbanov In-Reply-To: <1657886366-32685-1-git-send-email-quic_krichai@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 7/15/22 14:59, Krishna chaitanya chundru wrote: > Allow L1 and its sub-states in the qcom pcie driver. > By default this is disabled in the qcom specific hardware. > So enabling it explicitly only for controllers belonging to > 2_7_0. > > This patch will not affect any link capability registers, this > will allow the link transitions to L1 and its sub states only > if they are already supported. > > Signed-off-by: Krishna chaitanya chundru > Reviewed-by: Manivannan Sadhasivam > ---- > > Changes since v1 & v2: > - Update in the commit text only. > --- > drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++ > 1 file changed, 8 insertions(+) Acked-by: Stanimir Varbanov > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index a7202f0..5ef444f 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -41,6 +41,9 @@ > #define L23_CLK_RMV_DIS BIT(2) > #define L1_CLK_RMV_DIS BIT(1) > > +#define PCIE20_PARF_PM_CTRL 0x20 > +#define REQ_NOT_ENTR_L1 BIT(5) > + > #define PCIE20_PARF_PHY_CTRL 0x40 > #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) > #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) > @@ -1261,6 +1264,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > val |= BIT(4); > writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > + /* Enable L1 and L1ss */ > + val = readl(pcie->parf + PCIE20_PARF_PM_CTRL); > + val &= ~REQ_NOT_ENTR_L1; > + writel(val, pcie->parf + PCIE20_PARF_PM_CTRL); > + > if (IS_ENABLED(CONFIG_PCI_MSI)) { > val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > val |= BIT(31); -- regards, Stan