Re: [PATCH v4 01/13] x86/resctrl: Fix min_cbm_bits for AMD

James Morse
2022-09-09T17:01:11Z

Hi Babu,

On 07/09/2022 18:59, Babu Moger wrote:
> AMD systems support zero CBM (capacity bit mask) for L3 allocation.
> That is reflected in rdt_init_res_defs_amd() by:
>
> r->cache.arch_has_empty_bitmaps = true;
>
> However given the unified code in cbm_validate(), checking for:
> val == 0 && !arch_has_empty_bitmaps
>
> is not enough because of another check in cbm_validate():
>
> if ((zero_bit - first_bit) < r->cache.min_cbm_bits)

Right, the Intel version had this, but the AMD didn't. I evidently only thought about this
the !arch_has_empty_bitmaps way round! Sorry about that.

> The default value of r->cache.min_cbm_bits = 1.
>
> Leading to:
>
> $ cd /sys/fs/resctrl
> $ mkdir foo
> $ cd foo
> $ echo L3:0=0 > schemata
> -bash: echo: write error: Invalid argument
> $ cat /sys/fs/resctrl/info/last_cmd_status
> Need at least 1 bits in the mask
>
> Fix the issue by initializing the min_cbm_bits to 0 for AMD. Also,
> remove the default setting of min_cbm_bits and initialize it separately.
>
> After the fix
> $ cd /sys/fs/resctrl
> $ mkdir foo
> $ cd foo
> $ echo L3:0=0 > schemata
> $ cat /sys/fs/resctrl/info/last_cmd_status
> ok
>
> Link: https://lore.kernel.org/lkml/20220517001234.3137157-1-eranian@google.com/
> Fixes: 316e7f901f5a ("x86/resctrl: Add struct rdt_cache::arch_has_{sparse, empty}_bitmaps")

> Signed-off-by: Stephane Eranian <eranian@google.com>
> Signed-off-by: Babu Moger <babu.moger@amd.com>

Er, who is the author if this patch? If you are reposting Stephane's patch then there
needs to be a 'From: ' at the top of the email so that git preserves the ownership. You
may need some incantation of "git commit --amend --author=" to fix this in your tree.

As its a fix, have you posted this separately? Mixing fixes and new-code makes it hard for
the maintainer to spot what needs to be taken for the next -rc.

> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
> index bb1c3f5f60c8..a5c51a14fbce 100644
> --- a/arch/x86/kernel/cpu/resctrl/core.c
> +++ b/arch/x86/kernel/cpu/resctrl/core.c
> @@ -66,9 +66,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
> .rid = RDT_RESOURCE_L3,
> .name = "L3",
> .cache_level = 3,
> - .cache = {
> - .min_cbm_bits = 1,
> - },
> .domains = domain_init(RDT_RESOURCE_L3),
> .parse_ctrlval = parse_cbm,
> .format_str = "%d=%0*x",
> @@ -83,9 +80,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
> .rid = RDT_RESOURCE_L2,
> .name = "L2",
> .cache_level = 2,
> - .cache = {
> - .min_cbm_bits = 1,
> - },
> .domains = domain_init(RDT_RESOURCE_L2),
> .parse_ctrlval = parse_cbm,
> .format_str = "%d=%0*x",
> @@ -877,6 +871,7 @@ static __init void rdt_init_res_defs_intel(void)
> r->cache.arch_has_sparse_bitmaps = false;
> r->cache.arch_has_empty_bitmaps = false;
> r->cache.arch_has_per_cpu_cfg = false;
> + r->cache.min_cbm_bits = 1;
> } else if (r->rid == RDT_RESOURCE_MBA) {
> hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;
> hw_res->msr_update = mba_wrmsr_intel;
> @@ -897,6 +892,7 @@ static __init void rdt_init_res_defs_amd(void)
> r->cache.arch_has_sparse_bitmaps = true;
> r->cache.arch_has_empty_bitmaps = true;
> r->cache.arch_has_per_cpu_cfg = true;
> + r->cache.min_cbm_bits = 0;
> } else if (r->rid == RDT_RESOURCE_MBA) {
> hw_res->msr_base = MSR_IA32_MBA_BW_BASE;
> hw_res->msr_update = mba_wrmsr_amd;
>
>

Reviewed-by: James Morse <james.morse@arm.com>

Thanks,

James