Re: [PATCH v4 05/13] x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag

Reinette Chatre
2022-09-16T15:55:54Z

Hi Babu,

On 9/7/2022 11:00 AM, Babu Moger wrote:
> Newer AMD processors support the new feature Bandwidth Monitoring Event
> Configuration (BMEC).
>
> Support of this feature is available via CPUID Fn8000_0020_EBX_x0 (ECX=0).
> Bits Field Name Description
> 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC)
>
> Currently, the bandwidth monitoring events mbm_total_bytes and
> mbm_local_bytes are set to count all the total and local reads/writes
> respectively. With the introduction of SLOW memory, the two counters are

Why is SLOW in caps?

> not enough to count all the different types of memory events. With the
> feature BMEC, the users have the option to configure mbm_total_bytes and
> mbm_local_bytes to count the specific type of events.
>
> Each BMEC event has a configuration MSR, QOS_EVT_CFG (0x000_0400h +
> EventID) which contains one field for each Bandwidth Type that can be used
> to configure the bandwidth event to track any combination of supported
> bandwidth types. The event will count requests from every Bandwidth Type
> bit that is set in the corresponding configuration register.
>
> Following are the types of events supported:
>
> ==== ========================================================
> Bits Description
> ==== ========================================================
> 6 Dirty Victims from the QOS domain to all types of memory
> 5 Reads to slow memory in the non-local NUMA domain
> 4 Reads to slow memory in the local NUMA domain
> 3 Non-temporal writes to non-local NUMA domain
> 2 Non-temporal writes to local NUMA domain
> 1 Reads to memory in the non-local NUMA domain
> 0 Reads to memory in the local NUMA domain
> ==== ========================================================
>
> By default, the mbm_total_bytes configuration is set to 0x7F to count
> all the event types and the mbm_local_bytes configuration is set to
> 0x15 to count all the local memory events.
>
> Feature description is available in the specification, "AMD64 Technology
> Platform Quality of Service Extensions, Revision: 1.03 Publication # 56375
> Revision: 1.03 Issue Date: February 2022".
>
> Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-quality-service-extensions
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> Reviewed-by: Ingo Molnar <mingo@kernel.org>
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/kernel/cpu/scattered.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 1815435c9c88..a4ee02a56d54 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -305,6 +305,7 @@
> #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */
> #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
> #define X86_FEATURE_SMBA (11*32+18) /* SLOW Memory Bandwidth Allocation */
> +#define X86_FEATURE_BMEC (11*32+18) /* AMD Bandwidth Monitoring Event Configuration (BMEC) */

(numbering issue has already been discussed)

>
> /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
> #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> index 885ecf46abb2..7981df0b910e 100644
> --- a/arch/x86/kernel/cpu/scattered.c
> +++ b/arch/x86/kernel/cpu/scattered.c
> @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = {
> { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
> { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
> { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },
> + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
> { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
> { 0, 0, 0, 0, 0 }
> };
>
>

Similar to previous - please use same coding style as area being changed.

Is there a feature dependency (cpuid_deps[]) on X86_FEATURE_CQM_LLC needed?

Reinette