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From: Lu Baolu <baolu.lu@linux.intel.com>
To: "Liu, Yi L" <yi.l.liu@intel.com>, Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: baolu.lu@linux.intel.com, "Raj, Ashok" <ashok.raj@intel.com>,
	"Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
	"Pan, Jacob jun" <jacob.jun.pan@intel.com>,
	"Tian, Kevin" <kevin.tian@intel.com>,
	"Sun, Yi Y" <yi.y.sun@intel.com>,
	"peterx@redhat.com" <peterx@redhat.com>,
	Jean-Philippe Brucker <jean-philippe.brucker@arm.com>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: Re: [PATCH v4 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes
Date: Thu, 8 Nov 2018 10:22:14 +0800	[thread overview]
Message-ID: <855f56ac-80be-8179-ba99-45ef99ccb87f@linux.intel.com> (raw)
In-Reply-To: <A2975661238FB949B60364EF0F2C257439D5FAE7@SHSMSX104.ccr.corp.intel.com>

Hi,

On 11/7/18 2:55 PM, Liu, Yi L wrote:
> Hi Baolu,
> 
>> From: Lu Baolu [mailto:baolu.lu@linux.intel.com]
>> Sent: Monday, November 5, 2018 1:32 PM
>> Subject: [PATCH v4 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes
>>
>> Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid
>> entry for first-level or pass-through translation should be
>> programmed with a domain id different from those used for
>> second-level or nested translation. It is recommended that
>> software could use a same domain id for all first-only and
>> pass-through translations.
>>
>> This reserves a domain id for first-level and pass-through
>> translations.
>>
>> Cc: Ashok Raj <ashok.raj@intel.com>
>> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
>> Cc: Kevin Tian <kevin.tian@intel.com>
>> Cc: Liu Yi L <yi.l.liu@intel.com>
>> Cc: Sanjay Kumar <sanjay.k.kumar@intel.com>
>> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
>> ---
>>   drivers/iommu/intel-iommu.c | 10 ++++++++++
>>   drivers/iommu/intel-pasid.h |  6 ++++++
>>   2 files changed, 16 insertions(+)
>>
>> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
>> index 9331240c70b8..2f7455ee4e7a 100644
>> --- a/drivers/iommu/intel-iommu.c
>> +++ b/drivers/iommu/intel-iommu.c
>> @@ -1618,6 +1618,16 @@ static int iommu_init_domains(struct intel_iommu
>> *iommu)
>>   	 */
>>   	set_bit(0, iommu->domain_ids);
>>
>> +	/*
>> +	 * Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid
>> +	 * entry for first-level or pass-through translation modes should
>> +	 * be programmed with a domain id different from those used for
>> +	 * second-level or nested translation. We reserve a domain id for
>> +	 * this purpose.
>> +	 */
>> +	if (sm_supported(iommu))
>> +		set_bit(FLPT_DEFAULT_DID, iommu->domain_ids);
> 
> "FLPT_DEFAULT_DID" looks very likely for first level translation. How about
> "PT_FL_DEFAULT_DID"?

We have comments above it, so people won't be confused.

> 
>>   	return 0;
>>   }
>>
>> diff --git a/drivers/iommu/intel-pasid.h b/drivers/iommu/intel-pasid.h
>> index 12f480c2bb8b..03c1612d173c 100644
>> --- a/drivers/iommu/intel-pasid.h
>> +++ b/drivers/iommu/intel-pasid.h
>> @@ -17,6 +17,12 @@
>>   #define PDE_PFN_MASK			PAGE_MASK
>>   #define PASID_PDE_SHIFT			6
>>
>> +/*
>> + * Domain ID reserved for pasid entries programmed for first-level
>> + * only and pass-through transfer modes.
>> + */
>> +#define FLPT_DEFAULT_DID		1
> 
> Would be helpful to elaborate why DID 1 is selected in the patch
> description.

Yeah. DID 0 has been caved out for caching mode and we start from 1 for
this.

Best regards,
Lu Baolu

  reply	other threads:[~2018-11-08  2:24 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-05  5:31 [PATCH v4 00/12] iommu/vt-d: Add scalable mode support Lu Baolu
2018-11-05  5:31 ` [PATCH v4 01/12] iommu/vt-d: Enumerate the scalable mode capability Lu Baolu
2018-11-05  5:31 ` [PATCH v4 02/12] iommu/vt-d: Manage scalalble mode PASID tables Lu Baolu
2018-11-05  5:31 ` [PATCH v4 03/12] iommu/vt-d: Move page table helpers into header Lu Baolu
2018-11-07  7:41   ` Liu, Yi L
2018-11-05  5:31 ` [PATCH v4 04/12] iommu/vt-d: Add 256-bit invalidation descriptor support Lu Baolu
2018-11-07  6:07   ` Liu, Yi L
2018-11-08  2:16     ` Lu Baolu
2018-11-08  3:49       ` Liu, Yi L
2018-11-08  5:24         ` Lu Baolu
2018-11-08  5:45           ` Liu, Yi L
2018-11-08  6:14             ` Lu Baolu
2018-11-08  7:20               ` Liu, Yi L
2018-11-09  1:39                 ` Lu Baolu
2018-11-09  2:59                   ` Liu, Yi L
2018-11-08  5:48           ` Liu, Yi L
2018-11-08  6:15             ` Lu Baolu
2018-11-05  5:31 ` [PATCH v4 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes Lu Baolu
2018-11-07  6:55   ` Liu, Yi L
2018-11-08  2:22     ` Lu Baolu [this message]
2018-11-05  5:31 ` [PATCH v4 06/12] iommu/vt-d: Add second level page table interface Lu Baolu
2018-11-07  7:13   ` Liu, Yi L
2018-11-08  2:27     ` Lu Baolu
2018-11-08  4:00       ` Liu, Yi L
2018-11-05  5:31 ` [PATCH v4 07/12] iommu/vt-d: Setup pasid entry for RID2PASID support Lu Baolu
2018-11-05  5:31 ` [PATCH v4 08/12] iommu/vt-d: Pass pasid table to context mapping Lu Baolu
2018-11-07  7:25   ` Liu, Yi L
2018-11-08  2:34     ` Lu Baolu
2018-11-05  5:31 ` [PATCH v4 09/12] iommu/vt-d: Setup context and enable RID2PASID support Lu Baolu
2018-11-05  5:31 ` [PATCH v4 10/12] iommu/vt-d: Add first level page table interface Lu Baolu
2018-11-07  7:34   ` Liu, Yi L
2018-11-05  5:31 ` [PATCH v4 11/12] iommu/vt-d: Shared virtual address in scalable mode Lu Baolu
2018-11-05  7:15   ` Christoph Hellwig
2018-11-05  7:17     ` Lu Baolu
2018-11-05  5:31 ` [PATCH v4 12/12] iommu/vt-d: Remove deferred invalidation Lu Baolu

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