From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0B833EB810; Mon, 27 Jul 2026 09:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785144078; cv=none; b=dPn3soXWkbBn81fH12urQ66DgUrwRt34zbh/KRjEv0mbPc+Mgsger0WoKda332p//imwdC/pQdHKHdzyx/vs1We/xw3y09GC1EoArtmehM7RIwysj40oGJ9hnMGarzPQipMxsL1CsRPcRi3qUqb2XPZAq2Mv1y2URMF5XDfYLcE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785144078; c=relaxed/simple; bh=ADbGw0tGoLc0Gg6rKLnp+K2qMiplgwL6Iw1BbIxdaxM=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=lk4KbnM6Qn1G2ba8XwzPasr2Tq3qjuz7vBqrt8G0BpqD/Vl50adKutl/cRrg7+cQNvk9UxHbC9QDTCVlHo6kpSuZjACBlhks1/A5AiwXV29EXtI0PXiTCmfoS6POyLhey3xX8oKfcFSEOWxdI8K8ANb8gLUL2PfIM2VwWLOEAfE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kqjq8arZ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kqjq8arZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4ED521F000E9; Mon, 27 Jul 2026 09:21:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785144077; bh=FuhAGT2SliXe9B/N8fQVPhd+jv0ZqrbmY3LX55yWLPo=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=Kqjq8arZqZot8Vn0ynnS69jZo3ymclV2N6I0IZq3nSo4mJHi0a2p1po4oim1jRl8I AQQnmE+d4RwGy8kq6LKokLO1i6gHtg4jktdxvLnHU2XvG7lvbxunP/lqdTSerpma3y oW0mlrp3QQnVRZbMiD5pQ5TM3QOsQRq7Nk0mju6e5t12JDDzTptIUbw+fv77XJfOAx vsuY29fh2iMhLUPdS10gYHlwwlXv53KIp4zB1kBAATepQyZWSLrQqxUjNuEreljQ0N nipozxIHwIQxA1qIJyyLnVstB1dJpQk4A5NEtXYBf1OIvudn8hR/VFQX024vncBivt sDrm2+e6+f0Cg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1woHWM-00000009B23-39NE; Mon, 27 Jul 2026 09:21:14 +0000 Date: Mon, 27 Jul 2026 10:21:14 +0100 Message-ID: <861pcoeqk5.wl-maz@kernel.org> From: Marc Zyngier To: Steven Price Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, Catalin Marinas , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: Re: [PATCH v15 13/37] KVM: arm64: CCA: Support timers in realm RECs In-Reply-To: <20260715142841.80544-14-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> <20260715142841.80544-14-steven.price@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: steven.price@arm.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, oliver.upton@linux.dev, suzuki.poulose@arm.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, joey.gouly@arm.com, alexandru.elisei@arm.com, christoffer.dall@arm.com, tabba@google.com, linux-coco@lists.linux.dev, gankulkarni@os.amperecomputing.com, gshan@redhat.com, sdonthineni@nvidia.com, alpergun@google.com, aneesh.kumar@kernel.org, fj0570is@fujitsu.com, vannapurve@google.com, WeiLin.Chang@arm.com, lpieralisi@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 15 Jul 2026 15:28:15 +0100, Steven Price wrote: > > The RMM keeps track of the timer while the realm REC is running, but on > exit to the normal world KVM is responsible for handling the timers. > > A later patch adds the support for propagating the timer values from the > exit data structure and calling kvm_realm_timers_update(). > > Signed-off-by: Steven Price > --- > Changes since v14: > * Special case in kvm_timer_vcpu_load()/kvm_timer_vcpu_put() the timer > handling. > Changes since v12: > * Adapt to upstream changes. > Changes since v11: > * Drop the kvm_is_realm() check from timer_set_offset(). We already > ensure that the offset is 0 when calling the function. > Changes since v10: > * KVM_CAP_COUNTER_OFFSET is now already hidden by a previous patch. > Changes since v9: > * No need to move the call to kvm_timer_unblocking() in > kvm_timer_vcpu_load(). > Changes since v7: > * Hide KVM_CAP_COUNTER_OFFSET for realm guests. > --- > arch/arm64/kvm/arch_timer.c | 38 +++++++++++++++++++++++++++++++++--- > include/kvm/arm_arch_timer.h | 2 ++ > 2 files changed, 37 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index 4155fe89b58a..fdd68f1f5b7b 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -482,6 +482,20 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, > timer_ctx); > } > > +void kvm_realm_timers_update(struct kvm_vcpu *vcpu) > +{ > + struct arch_timer_cpu *arch_timer = &vcpu->arch.timer_cpu; > + int i; > + > + for (i = 0; i < NR_KVM_EL0_TIMERS; i++) { > + struct arch_timer_context *timer = &arch_timer->timers[i]; > + bool status = timer_get_ctl(timer) & ARCH_TIMER_CTRL_IT_STAT; > + bool level = kvm_timer_enabled(timer) && status; > + > + kvm_timer_update_irq(vcpu, level, timer); > + } > +} > + Why do we need this? What is so special about CCA that it cannot use the existing timer flow? > /* Only called for a fully emulated timer */ > static void timer_emulate(struct arch_timer_context *ctx) > { > @@ -888,6 +902,11 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) > if (unlikely(!timer->enabled)) > return; > > + if (vcpu_is_rec(vcpu)) { > + kvm_timer_unblocking(vcpu); > + return; > + } > + > get_timer_map(vcpu, &map); > > if (static_branch_likely(&has_gic_active_state)) { > @@ -923,6 +942,12 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) > if (unlikely(!timer->enabled)) > return; > > + if (vcpu_is_rec(vcpu)) { > + if (kvm_vcpu_is_blocking(vcpu)) > + kvm_timer_blocking(vcpu); > + return; > + } > + > get_timer_map(vcpu, &map); > > timer_save_state(map.direct_vtimer); > @@ -1073,7 +1098,7 @@ static void timer_context_init(struct kvm_vcpu *vcpu, int timerid) > > ctxt->timer_id = timerid; > > - if (!kvm_vm_is_protected(vcpu->kvm)) { > + if (!kvm_vm_is_protected(vcpu->kvm) && !vcpu_is_rec(vcpu)) { > if (timerid == TIMER_VTIMER) > ctxt->offset.vm_offset = &kvm->arch.timer_data.voffset; > else > @@ -1104,7 +1129,7 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) > timer_context_init(vcpu, i); > > /* Synchronize offsets across timers of a VM if not already provided */ > - if (!vcpu_is_protected(vcpu) && > + if (!vcpu_is_protected(vcpu) && !vcpu_is_rec(vcpu) && > !test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) { > timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read()); > timer_set_offset(vcpu_ptimer(vcpu), 0); > @@ -1600,6 +1625,13 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) > return -EINVAL; > } > > + /* > + * We don't use mapped IRQs for Realms because the RMI doesn't allow > + * us setting the LR.HW bit in the VGIC. > + */ > + if (vcpu_is_rec(vcpu)) > + return 0; > + If you can't set the HW bit, then use the existing infrastructure for similarly challenged systems. But I find this restriction hard to swallow. What is so special about the HW bit? As it stands, I don't think this is acceptable, and I really want to know why you need to special-case the timer code. M. -- Without deviation from the norm, progress is not possible.