From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE617153BD2; Fri, 3 May 2024 15:50:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714751407; cv=none; b=KUnjAHuV4KdeMLLdc5kH13kVpp439T++RSVkATECh/yt9sjjTfN1HhMCE0vRuZse0/3bgB1nYKqv7qpOHNuTellTW5nbSO4Y+kuvOGweRRQNHOSpfIrwHm1lqjmcInerQ1Wq75jZiuTOhXPldd6Apxtn220Xsj5GRyVAgfEbivo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714751407; c=relaxed/simple; bh=tTf3/I0X6noSsL8gZHpFvXAa4w9S4bunYn6yomXXBdM=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=mPb9/h4GgE+uCSJLhAfVz0EaylthvutDToS6nyZTI65KVdFtA/um/xAQZzWrPrjXPBAQCGge8xNH/yB881wWcWp+WEbmF6KcaNKEAq/SOtfMeOU5/B0cw3QJrPJmHbt6TUwW5ToCvBu62tYUU8o0DUaekgNJdZCle2o6id6PMas= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iNK6FH1L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iNK6FH1L" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64500C116B1; Fri, 3 May 2024 15:50:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714751406; bh=tTf3/I0X6noSsL8gZHpFvXAa4w9S4bunYn6yomXXBdM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=iNK6FH1LE+MtkOwLevF0WKa3r6EyZrc8Ksw5D6b4NRT1ACAAKqR0ufV+EkSRC0mXd ztBvbaYc/d90Dzc4KwJgFMK3LHTOmF8LUS7xKqstuv6CM9mR+M5lvdAgpiUp1jah5G b61B7Gbn9qh1cvws0ys7zZJo53f3nw026/OffLggc3Tm5J/wfN049wEXax+k7sdRpY 1kriaM0ZBALdQBlrluWDSeJUAEhN6Vh2x408O55lNO9EUhsepqQ6OZQ+vkgyJAT0BC zKIQ3fah6/mJmGEcSD6EAbnSqcBdPlechsOsx6/3wwN72teRupRvneRPdaSDtj+1B5 uuOLXf6snqzNg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1s2vAi-00AMxN-1J; Fri, 03 May 2024 16:50:04 +0100 Date: Fri, 03 May 2024 16:50:02 +0100 Message-ID: <861q6irj2t.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: Sebastian Ott , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon Subject: Re: [PATCH v2 4/6] KVM: arm64: add emulation for CTR_EL0 register In-Reply-To: References: <20240426104950.7382-1-sebott@redhat.com> <20240426104950.7382-5-sebott@redhat.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, sebott@redhat.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, catalin.marinas@arm.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 01 May 2024 09:15:09 +0100, Oliver Upton wrote: > > On Fri, Apr 26, 2024 at 12:49:48PM +0200, Sebastian Ott wrote: > > CTR_EL0 is currently handled as an invariant register, thus > > guests will be presented with the host value of that register. > > > > Add emulation for CTR_EL0 based on a per VM value. Userspace can > > switch off DIC and IDC bits and reduce DminLine and IminLine sizes. > > > > When CTR_EL0 is changed validate that against CLIDR_EL1 and CCSIDR_EL1 > > to make sure we present the guest with consistent register values. > > Changes that affect the generated cache topology values are allowed if > > they don't clash with previous register writes. > > Sorry I didn't speak up earlier, but I'm not sold on the need to > cross-validate userspace values for the cache type registers. > > KVM should only be concerned about whether or not the selected feature > set matches what hardware is capable of and what KVM can virtualize. So > in the context of the CTR and the cache topology, I feel that they > should be _separately_ evaluated against the host's CTR_EL0. > > Inconsistencies between fields in userspace values should be out of > scope; userspace shares the responsibility of presenting something > architectural, especially if it starts modifying ID registers. Otherwise > I'm quite worried about the amount of glue required to plumb exhaustive > consitency checks for registers, especially considering the lack of > ordering. > > Marc, I know this goes against what you had suggested earlier, is there > something in particular that you think warrants the consistency > checks? The problem is that we have a dependency chain: individual cache levels are validated against CLIDR/CCSIDR, which are themselves validated against CTR_EL0. Change one, and everything becomes inconsistent. I absolutely don't trust userspace to do a good job on that, and not validating this will result in extremely hard to debug issues in the guest. Which is why CTR_EL0 was an invariant the first place, and everything derived from it. Take for example CLIDR_EL1.Lo{UU,UIS,C}. Their values depend on CTR_EL0.{IDC,DIC}. SW is free to check one or the other. If you don't have this dependency, you're in for some serious trouble. The alternative is to *regenerate* the whole cache hierarchy when CTR_EL0 is written, and too bad if it changes behind the guest's back. Yes, the latter is a problem on its own... Thanks, M. -- Without deviation from the norm, progress is not possible.