From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D0B4CD13D8 for ; Mon, 18 Sep 2023 12:57:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241667AbjIRM5d (ORCPT ); Mon, 18 Sep 2023 08:57:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241588AbjIRM5A (ORCPT ); Mon, 18 Sep 2023 08:57:00 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6075FA8 for ; Mon, 18 Sep 2023 05:56:55 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F1510C433C8; Mon, 18 Sep 2023 12:56:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695041815; bh=PQ12Teyfc+RzCK1vh1Mh8c932ain1F5sReUBIdCQlqU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=oCkjTg3dtcDupIPuTpuYyIQ19Mm62dVrhhN7F6ZaeX3zaeg4gqDo2EQdPrVM9HHGZ hKJdpzeJNCpFfG3xBle++vISZrCbriFC2WLrY2N218JAOGisYb+1hnnP3uIgpr1fgo eUsAbvyFGekR/YmcJLfxydI2iDyCIkR8nvGU0dU8dYUaX9sT73cFeoHfwOX+5qixr+ qmY0WD7OXtBQ5Ju4qvzRntPeW3xBk/3+vLXcvdqD8kSci+22VNzKyfOwLE/w99XLaM NPmYBnX2am3l7qkzTvOtO2njX4/eTuMCpLd6MSR8JPVqX2VjENmlolJYvZZbBYgtVI O6+vfubsGv6sQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qiDo4-00Dy7d-CC; Mon, 18 Sep 2023 13:56:52 +0100 Date: Mon, 18 Sep 2023 13:56:51 +0100 Message-ID: <861qevej1o.wl-maz@kernel.org> From: Marc Zyngier To: Miguel Luis Cc: Catalin Marinas , Will Deacon , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "kvmarm@lists.linux.dev" Subject: Re: [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers In-Reply-To: <4A24B4EC-B221-48B6-BA91-DB7AC72CAA8D@oracle.com> References: <20230913185209.32282-1-miguel.luis@oracle.com> <20230913185209.32282-4-miguel.luis@oracle.com> <867conerys.wl-maz@kernel.org> <4A24B4EC-B221-48B6-BA91-DB7AC72CAA8D@oracle.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: miguel.luis@oracle.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 18 Sep 2023 13:41:45 +0100, Miguel Luis wrote: > > Hi Marc, > > > On 18 Sep 2023, at 09:44, Marc Zyngier wrote: > > > > On Wed, 13 Sep 2023 19:52:08 +0100, > > Miguel Luis wrote: > >> > >> Specify both _EL02 and _EL12 system registers. > >> > >> Signed-off-by: Miguel Luis > >> --- > >> arch/arm64/kvm/emulate-nested.c | 35 +++++++++++++++++++++++++++++---- > >> 1 file changed, 31 insertions(+), 4 deletions(-) > >> > >> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > >> index 9aa1c06abdb7..957afd97e488 100644 > >> --- a/arch/arm64/kvm/emulate-nested.c > >> +++ b/arch/arm64/kvm/emulate-nested.c > >> @@ -690,10 +690,37 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { > >> SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3), > >> sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV), > >> /* All _EL02, _EL12 registers */ > >> - SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), > >> - sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), > >> - SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0), > >> - sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV), > >> + SR_TRAP(SYS_SCTLR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_CPACR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_SCTLR2_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_ZCR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_TRFCR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_SMCR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_TTBR0_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_TTBR1_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_TCR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_TCR2_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_SPSR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_ELR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_AFSR0_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_AFSR1_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_ESR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_TFSR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_FAR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_BRBCR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_PMSCR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_MAIR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_AMAIR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_VBAR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_CONTEXTIDR_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_SCXTNUM_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_CNTKCTL_EL12, CGT_HCR_NV), > >> + SR_TRAP(SYS_CNTP_TVAL_EL02, CGT_HCR_NV), > >> + SR_TRAP(SYS_CNTP_CTL_EL02, CGT_HCR_NV), > >> + SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_HCR_NV), > >> + SR_TRAP(SYS_CNTV_TVAL_EL02, CGT_HCR_NV), > >> + SR_TRAP(SYS_CNTV_CTL_EL02, CGT_HCR_NV), > >> + SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_HCR_NV), > >> SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV), > >> SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV), > >> SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV), > > > > While I could see the problem with the EL2 registers, I'm not > > convinced by this patch. Is there an actual case for non _EL02, non > > _EL12 registers that are included in the two ranges above? > > > > Having DDI0487Ja as reference, there is none. It is not clear to me having two > separate ranges. If it is to cover _EL02 and _EL12 ranges separately then the > second range is covering both aliases. I couldn't find the reason for these > aliases start and end other than SYS_SCTLR_EL12 and SYS_CNTV_CVAL_EL02, > respectively. The reason we have two ranges is to explicitly exclude the IMPDEF range, which is trapped by HCR_EL2.TIDCP: SR_RANGE_TRAP(sys_reg(3, 5, 11, 0, 0), sys_reg(3, 5, 11, 15, 7), CGT_HCR_TIDCP), Thanks, M. -- Without deviation from the norm, progress is not possible.