From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8131C2C6B7; Tue, 2 Jul 2024 10:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719917884; cv=none; b=g/1RIhVeY5KVBy+HzKr9p475VnbvD3Cm/BJ0Ng1BevTXG2ESB/f8n9k/3LWjW2l6/8Y4YYMNbqSzMefkNRPi9r/UthcwkRLVNf2HUeTqf59xuuuBL3NNT+yWmHYsW540Gy+Ifpnb+B8hKehX/QFwe2+flft1Ko7y2z0LfqHgDjE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719917884; c=relaxed/simple; bh=rrCVXKvoyxrAjTZibby6tyssNtKkAiDxJiikT8VGUmo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Tlva4nRCps6mk4Lu0EigmGzCukcplN2x8bIu5pJwnySJHvmwtpajairP+w8xUUFpD4zhqAM2QKpy5KDVTpXDgrtZqgfaxtrzRcOiC4VSe+p7JIIB9IPi9esTYJxA0vbBApau7M5MNMN6pPJjibW1z9bd2aX+49SfmN7GK92nd70= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F6dj6Cdp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F6dj6Cdp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E209C116B1; Tue, 2 Jul 2024 10:58:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719917884; bh=rrCVXKvoyxrAjTZibby6tyssNtKkAiDxJiikT8VGUmo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=F6dj6Cdp+pNANzFdsIvbbIfU3A6Z8nyXITbiVxrVehZrbSCOjjDRYh4zOvUT0fIVu 3zvQ03s416MddWLQh86UN7zJ+ewAEeJyCKiVyZxEHRGJquvJsufM6h4n3/yTx6cnyh lKhcInPoJkK8ho9gCNO7OsQJarA+J85DOp8ScDfPkWOTRCFK+bW0oIcR7effym4hbM gwDHyyfxZh9JYkMtfo4CL53bYHn/dEfqYKPNqtz8bpNxj0glfIb+7IG9KLY8vRMyU4 vZBLtbZk6gRjjPp5eG8a+PGt/VC0aiqin1k8QiX/EbZfWpn2pkg1UQeTN0gtLOA0gf 1mSr+JrFSVypQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sObCz-0094im-I8; Tue, 02 Jul 2024 11:58:01 +0100 Date: Tue, 02 Jul 2024 11:58:00 +0100 Message-ID: <8634oshxhj.wl-maz@kernel.org> From: Marc Zyngier To: Yangyu Chen Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, Mark Rutland , Janne Grunau , Hector Martin , Asahi Lina , asahi@lists.linux.dev, Linux Kernel Mailing List Subject: Re: [PATCH v1] drivers/perf: apple_m1: fix affinity table for event 0x96 and 0x9b In-Reply-To: References: <20240701140148.GE2250@willie-the-truck> <87cynxp52o.wl-maz@kernel.org> <87bk3hp3z7.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: cyy@cyyself.name, will@kernel.org, linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, j@jannau.net, marcan@marcan.st, lina@asahilina.net, asahi@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 02 Jul 2024 11:22:21 +0100, Yangyu Chen wrote: > > > Yangyu, can you please clarify how you came to the conclusion that > > these events didn't count anywhere other than counter 7? > > > > IIRC, I came across some web page that says events 0x96 and 0x9b > can only be installed on counter 7 to count Apple AMX, but I can't > find the page now. Since AMX is not usable in Linux, I don't know > if this will affect some other instructions that are usable in > Linux. As you said, AMX cannot be used with Linux, and that's unlikely to ever change. But when it comes to the standard ARM ISA, we can only witness counters 5,6 and 7 being incremented with at the exact same rate. So reading between the lines, what I understand is that AMX instructions would only have their effects counted in counter 7 for these events, while other instructions would be counted in all 3 counters. By extension, such behaviour could be applied to SME on HW that supports it (wild guess). > There are some other reasons, but I can't say in public. Fair enough, I'm not asking for the disclosure of anything that isn't public (the least I know, the better). > Even though I can't find the actual usage, I think using count 7 > only for these 2 events is safer. If this reason is insufficient, > we can ignore this patch until we find other evidence that this > affinity affects some instructions usable in Linux. I honestly don't mind. The whole thing is a black box, and is more useful as an interrupt generator than an actual PMU, due to the lack of freely available documentation. If the PMU maintainers want to merge this, I won't oppose it. Thanks, M. -- Without deviation from the norm, progress is not possible.