From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6FBFC761A6 for ; Mon, 3 Apr 2023 08:08:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231827AbjDCIIr (ORCPT ); Mon, 3 Apr 2023 04:08:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231634AbjDCIIj (ORCPT ); Mon, 3 Apr 2023 04:08:39 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B01B3C3E for ; Mon, 3 Apr 2023 01:08:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2E19A615C9 for ; Mon, 3 Apr 2023 08:08:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8F833C433EF; Mon, 3 Apr 2023 08:08:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680509296; bh=/+W+JvdxzT4I41elESOo7q4RSlWmDtw8Jj0yqh5T878=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=YbGjB3A6lt/GJIwSlisc+gZNUQeLpWGqoHlBQtG74xbFHCnQ2r7s16uEZKjkwKzmh vsJ0SviaEMx86s9NB8aDIZpDB6Yx3cDjH/iurFN927eoBgJ2wNiNUqQjOQpa+0T84H iNSvgZfAsYOgk4cpaLjBWMujMLlTA7BhRI7ds0XI9ZCHWQO2bNU8GqViH/lWCpDJZG a/xMeUC0pj/I5jrvuSs+xSDmzsE/jEoVjk3RXA/meDJ9VHBKIZ79VOUoyz+FPJLgnW QSr2DPwqfoGaslB10m1NrYTuY5hCdj/n/otkl9TiZKwjh0Z+5WnytZr8epQwcJa/TR O54iahFByr3mA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pjFEc-005EV6-Bc; Mon, 03 Apr 2023 09:08:14 +0100 Date: Mon, 03 Apr 2023 09:08:13 +0100 Message-ID: <86355hwfpu.wl-maz@kernel.org> From: Marc Zyngier To: Peng Fan Cc: Lorenzo Pieralisi , "linux-kernel@vger.kernel.org" Subject: Re: gic700 shareability question In-Reply-To: References: <868rfdw797.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: peng.fan@nxp.com, lpieralisi@kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 03 Apr 2023 02:36:31 +0100, Peng Fan wrote: > > Hi Marc, > > > Subject: Re: gic700 shareability question > > > > + Lorenzo > > > > On Tue, 28 Mar 2023 13:48:19 +0100, > > Peng Fan wrote: > > > > > > Hi Marc, > > > > > > We have an SoC that use GIC-700, but not support shareability, > > > > Define this. The IP does support shareability, but your integration doesn't? > > > > > Currently I just hack the code as below. Do you think it is feasible > > > to add firmware bindings such that these can be used to define the > > > correct shareability/cacheability instead of relying on the > > > programmability of the CBASER register? > > > > > > Saying with "broken-shareability", we just clear all the shareability > > > settings. > > > > This is the same thing as the Rockchip crap, so you are in good company. > > > > I've repeatedly stated that this needs to be handled: > > > > - either by describing the full system topology and describe what is > > in the same inner-shareable domain as the CPUs, which needs to > > encompass both DT and ACPI (starting with DT seems reasonable), > > > > We will give a look on this. But honestly not have a good idea on how. For each node that can initiate memory transactions in the system, you have a phandle to a node that describe the shareability. In your case, you would have two nodes: one inner-shareable with at least the CPUs and whatever IP block that is in the same IS domain, and another that describe the outer-shareable domain. Or another variation on the same theme. M. -- Without deviation from the norm, progress is not possible.