From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDF823AA1A2 for ; Wed, 1 Apr 2026 08:15:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775031333; cv=none; b=W3HUMkjy1DE1x2oOQ0hQTrR5ZguWZ4UZ2X0ivuJn5Hq+rVMDgdQ8OIbm8r5kKDHHV88CUlwmVZ9EEvExCGxMB5+xrJ55e9sT1XA0B+xp9WxKSnJv1bAgEI/RgSAix8j1kzU+vbtprdESkS5UsPAA37nSpAEfD9Fx9xnGn+pwWRI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775031333; c=relaxed/simple; bh=eilOPkOqHm1EaOKW0H+rd4Q2yZqsOd8qWXFZtwa0vqQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=OiK/ERlhBeNZXqlwCi9D7b1IOWIpqZp0+j9afHtUDiYvACTzcEE3lkNWjSVfJUQBBI0b5cVqk4rp1qLu36HpZ2r5sWwNH1LEnbQYodfIkp6nVNPAL1UdxCfoGN7WtumQEzPilVXL14GxJsQEfPqwJLBdFOh1pFjDOB36UFqAjT8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OxiEe9u8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OxiEe9u8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8277FC4CEF7; Wed, 1 Apr 2026 08:15:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775031332; bh=eilOPkOqHm1EaOKW0H+rd4Q2yZqsOd8qWXFZtwa0vqQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=OxiEe9u8oUHimWsjbzhRgpiXgC6XgPRjrOUHYUm2iK3BdChM6hiegtIhC2uYShHMb gRrCgQjjTdoOKdnWpaotVnFwKCC/ASx0yMqFNMJx11MQlWhZG9q6H1XOvVJNCOsXtB 9Dg0gp4g58J8/tGoxXF6beBP5j8IFVly0uIir2Mo72YdShl0E8c5c+wSJj9NLK95Nz yg7BcohWSMiChMwpn9Xnj14MVAg0SPQfgBAGvd7oeIXzmpYc4KHqYVIsuT7eg41Lv2 +jzVPnXepyXiY34cdB88nBkrFHBZZMoWq0T+JRC/8H5GqLjo7ZjjnoVSUeb97m7seH bhDC0tzPLrYOQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w7qja-00000007l46-1Zsb; Wed, 01 Apr 2026 08:15:30 +0000 Date: Wed, 01 Apr 2026 09:15:30 +0100 Message-ID: <864ilv3xlp.wl-maz@kernel.org> From: Marc Zyngier To: Manivannan Sadhasivam Cc: Qiang Yu , tglx@linutronix.de, linux-kernel@vger.kernel.org Subject: Re: MSIs not freed in GICv3 ITS driver In-Reply-To: References: <865xtf4woi.wl-maz@kernel.org> <20240709173708.GA44420@thinkpad> <877cdupdvu.wl-maz@kernel.org> <20240721085032.GL1908@thinkpad> <4pdu25dnnqegnd67zf4ftfvwc57bn67kp7mj2gk2cywc3hdcvr@eydar5gvuwtu> <86wm08ad2y.wl-maz@kernel.org> <865x7jaajs.wl-maz@kernel.org> <86cy0l4tq1.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mani@kernel.org, qiang.yu@oss.qualcomm.com, tglx@linutronix.de, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 01 Apr 2026 08:59:02 +0100, Manivannan Sadhasivam wrote: > > On Mon, Mar 30, 2026 at 09:17:10AM +0100, Marc Zyngier wrote: > > On Tue, 03 Mar 2026 09:26:32 +0000, > > Manivannan Sadhasivam wrote: > > > > > > The above issue should be applicable to other MSI controller drivers as well, > > > not just DWC. > > > > The core issue is not with the irqchips, but with the MSI subsystem. > > > > Multi-MSI devices should always result in a strict power-of-2 > > allocation, because that's all the HW supports. Yet, we let drivers > > request a stupid number of interrupts. > > > > I can see two outcomes: either we force the allocation to the next 2^ > > value, or we return an error to the caller. The first one costs memory > > (extra irq descriptors), the latter forces people to fix their crap. > > > > I'm tempted to propose the latter. > > > > That might cause a lot of regressions I believe. IMO, safe bet would be to > handle the power of 2 allocations inside the irqchip drivers. What part of "this is a violation of the PCI spec" did you miss? I didn't realise we were in the business of adding crap just because endpoint drivers are broken. In any case, I'm not touching the ITS driver. M. -- Without deviation from the norm, progress is not possible.