From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1DCB1459FA; Wed, 25 Jun 2025 16:45:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750869909; cv=none; b=D0KILTmPwg3Wq3+iRLKAyNtkf7phoXr9fTaWyeO75iYh0h8IX/DQs+1vbc+ndiLZ92w3CK0uMNm2nZ2hOAKFdgMPA9uAVXWsj+gayKtMS9Rn01G3dJuOtMh2IUzfHUb7pVCWsQBmlt4oB9TNNfBMsE6t1ZJa9PkfoLIVltbvmps= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750869909; c=relaxed/simple; bh=eHt7/sdhBm2wrbfo5b0J8+QgVHCBsUd1GoFda8/mRSc=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=P+4s1z5wKuPC9TJ4AQ88XUwJAamE+oiyeqv7UDcnbxByeohYzjRyo+H4DtOI2a5iPXkYj+rpyUXZKoZjVZmXdnciRXfleyoAMSKDl/rDhyNEZwqWWxvCHl9UlXGhRrkDx1aNrlDfbtg2Yha2+KfSWcym7/dh2ewK/1fIi+KuvyM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q9GKGrT3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q9GKGrT3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 398E5C4CEEA; Wed, 25 Jun 2025 16:45:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750869909; bh=eHt7/sdhBm2wrbfo5b0J8+QgVHCBsUd1GoFda8/mRSc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Q9GKGrT3HeuuBaZWhCu55yO6hFWUgZ/cQ+j5PCUiakBE2ABS86kqUWg+8/BqpkJr/ hl4j9mOnMVadU8WXJuNm3BQ/fjaPx4B13//DEJU/hxyqZPad89TEL4zfsaA5cKMvrm BI2lSzhdJdsyookX3FSqyx2ASMzYwYXvD3zCoSJIa0BEn6TbdRftT1mYKa6u24QgA3 IDPBX9cXJpYFw3GUxLSaEDXQvwh6e/0M5Vwosi8njgwImWGTkqzTM25T2+HqHu993X R5egqU0E3VS41dzlwqodzZtYHgUhdS/yw+qwct1KvX6xIG61nVmFPN5VmpbWK3iNRt tPNkqBoN8lrTQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uUTFC-009xzP-Iu; Wed, 25 Jun 2025 17:45:06 +0100 Date: Wed, 25 Jun 2025 17:45:06 +0100 Message-ID: <864iw3db3h.wl-maz@kernel.org> From: Marc Zyngier To: Wei-Lin Chang Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Jintack Lim , Christoffer Dall Subject: Re: [PATCH] KVM: arm64: nv: Fix MI line level calculation in vgic_v3_nested_update_mi() In-Reply-To: <20250625084709.3968844-1-r09922117@csie.ntu.edu.tw> References: <20250625084709.3968844-1-r09922117@csie.ntu.edu.tw> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: r09922117@csie.ntu.edu.tw, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, jintack@cs.columbia.edu, christoffer.dall@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 25 Jun 2025 09:47:09 +0100, Wei-Lin Chang wrote: > > The state of the vcpu's MI line should be asserted when its > ICH_HCR_EL2.En is set and ICH_MISR_EL2 is non-zero. Using bitwise AND > (&=) directly for this calculation will not give us the correct result > when the LSB of the vcpu's ICH_MISR_EL2 isn't set. Correct this by first > adjusting the return value of vgic_v3_get_misr() into 1 if it is > non-zero. > > Signed-off-by: Wei-Lin Chang > --- > arch/arm64/kvm/vgic/vgic-v3-nested.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c > index 4f6954c30674..ebffad632fd2 100644 > --- a/arch/arm64/kvm/vgic/vgic-v3-nested.c > +++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c > @@ -400,7 +400,7 @@ void vgic_v3_nested_update_mi(struct kvm_vcpu *vcpu) > > level = __vcpu_sys_reg(vcpu, ICH_HCR_EL2) & ICH_HCR_EL2_En; > if (level) > - level &= vgic_v3_get_misr(vcpu); > + level &= !!vgic_v3_get_misr(vcpu); > kvm_vgic_inject_irq(vcpu->kvm, vcpu, > vcpu->kvm->arch.vgic.mi_intid, level, vcpu); > } Very well spotted, once more. Where were you when I posted all these patches? ;-) We could make it even clearer with this: diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c index a50fb7e6841f7..679aafe77de2e 100644 --- a/arch/arm64/kvm/vgic/vgic-v3-nested.c +++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c @@ -401,9 +401,7 @@ void vgic_v3_nested_update_mi(struct kvm_vcpu *vcpu) { bool level; - level = __vcpu_sys_reg(vcpu, ICH_HCR_EL2) & ICH_HCR_EL2_En; - if (level) - level &= vgic_v3_get_misr(vcpu); + level = (__vcpu_sys_reg(vcpu, ICH_HCR_EL2) & ICH_HCR_EL2_En) && vgic_v3_get_misr(vcpu); kvm_vgic_inject_irq(vcpu->kvm, vcpu, vcpu->kvm->arch.vgic.mi_intid, level, vcpu); } If you're OK with it, I'll use this, keeping your authorship of course. Thanks, M. -- Without deviation from the norm, progress is not possible.