From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FA462144CF; Wed, 19 Feb 2025 17:45:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739987102; cv=none; b=iqozSCvvvFwMGMPp5DEShpKKQflaaFBivgP4/olEHCAsLR5EJn6gL7NrqAdaZAYJgiyMio/RAlXPTMwLzZWPfQcQiVvxjV3YYI4RlFShZQqLlF0724VeMt/BZcF0HWutMw9vaxY3sNze+jgrbU31erfKJGG19HD+oEUP6trBLJ4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739987102; c=relaxed/simple; bh=9DDQSRBXojYKs3E7l0ZcCaT7BmSFwinEFa+8YID+AY0=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=pBcE4vYr1FhYv4N5Ph71acGfG0+9eilxiHnMeWn5ti+B8RKbxW0cR6bUYoL8pUp9DxuLoBpVAgi81ymSau6VMvl9U2cVb5fNvL4OiGxUZM2uHITr43WcVgz9eL7Bp5iocP3zRqnGMD34wMr61YsvdleSxu3/43YGDL/Yt+LdbBw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GzI76u01; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GzI76u01" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E56B1C4CED1; Wed, 19 Feb 2025 17:45:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1739987102; bh=9DDQSRBXojYKs3E7l0ZcCaT7BmSFwinEFa+8YID+AY0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=GzI76u01W+GuItG8twFKvac3xBV8lqEt2O70ZlQ9ECAM7mn4PvY6B6m3dFVNeoSJF bAZxgh30RdMRUzQZLDVLSZOCrIsIbWzdIvS33u09PTY07HDgLbMXmj9W6psLwIPzV0 RRdB7by9dMs04GOCMFsJFA3aNWTLPeTIY3MtUfRUk7iI1rZlLhg6o8YHzQk6Y1myQG +vh8xwegNiTBcoB2O13Kb55jz5H6cBYN5tTbvKe6Xv5pKDYLJPngZcOJg79IpF7r1H 9Fe0p6n8xuhg2RWvpbnx4SRy/p+ijK15Cn73A1hkbadJEXNaZqwemj4H/B/dHrvYY/ i6Rd5VZq9xLKg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tko83-005ud8-MR; Wed, 19 Feb 2025 17:44:59 +0000 Date: Wed, 19 Feb 2025 17:44:59 +0000 Message-ID: <864j0psuas.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Janne Grunau Subject: Re: [PATCH v2 07/14] KVM: arm64: Use a cpucap to determine if system supports FEAT_PMUv3 In-Reply-To: <20250203183111.191519-8-oliver.upton@linux.dev> References: <20250203183111.191519-1-oliver.upton@linux.dev> <20250203183111.191519-8-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mizhang@google.com, coltonlewis@google.com, rananta@google.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, j@jannau.net X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 03 Feb 2025 18:31:04 +0000, Oliver Upton wrote: > > KVM is about to learn some new tricks to virtualize PMUv3 on IMPDEF > hardware. As part of that, we now need to differentiate host support > from guest support for PMUv3. > > Add a cpucap to determine if an architectural PMUv3 is present to guard > host usage of PMUv3 controls. > > Tested-by: Janne Grunau > Signed-off-by: Oliver Upton > --- > arch/arm64/include/asm/cpufeature.h | 5 +++++ > arch/arm64/kernel/cpufeature.c | 19 +++++++++++++++++++ > arch/arm64/kvm/hyp/include/hyp/switch.h | 4 ++-- > arch/arm64/kvm/pmu.c | 10 +++++----- > arch/arm64/tools/cpucaps | 1 + > include/kvm/arm_pmu.h | 2 +- > 6 files changed, 33 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index e0e4478f5fb5..0eff048848b8 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -866,6 +866,11 @@ static __always_inline bool system_supports_mpam_hcr(void) > return alternative_has_cap_unlikely(ARM64_MPAM_HCR); > } > > +static inline bool system_supports_pmuv3(void) > +{ > + return cpus_have_final_cap(ARM64_HAS_PMUV3); > +} > + > int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); > bool try_emulate_mrs(struct pt_regs *regs, u32 isn); > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 4eb7c6698ae4..6886d2875fac 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1898,6 +1898,19 @@ static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) > } > #endif > > +static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) > +{ > + u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); > + unsigned int pmuver; > + > + pmuver = cpuid_feature_extract_unsigned_field(dfr0, > + ID_AA64DFR0_EL1_PMUVer_SHIFT); > + if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) > + return false; > + > + return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; Given that PMUVer is a signed field, how about using cpuid_feature_extract_signed_field() and do a signed comparison instead? > +} > + > #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 > #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) > > @@ -2999,6 +3012,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) > }, > #endif > + { > + .desc = "PMUv3", > + .capability = ARM64_HAS_PMUV3, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .matches = has_pmuv3, > + }, This cap is probed unconditionally (without any configuration dependency)... > {}, > }; > > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h > index f838a45665f2..0edc7882bedb 100644 > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h > @@ -244,7 +244,7 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) > * counter, which could make a PMXEVCNTR_EL0 access UNDEF at > * EL1 instead of being trapped to EL2. > */ > - if (kvm_arm_support_pmu_v3()) { > + if (system_supports_pmuv3()) { ... but kvm_arm_support_pmu_v3() is conditional on CONFIG_HW_PERF_EVENTS. Doesn't this create some sort of new code path that we didn't expect? Thanks, M. -- Without deviation from the norm, progress is not possible.