From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9221B13BC18; Wed, 15 Jan 2025 15:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736954037; cv=none; b=A2s5jSjdHA5lfkheSBZWoHlVvxmz18YuCaeu79gFhyze+PF+hVdlK7DvhX1cr4hsHXZnHv11w99jhGt3RZtdxKo96o9nrbFBcDBXAkPP8p3WepsWSPwMOAYvDBGqZ3g4axqc2wSxXuTraPIlYuLl6YYC7OE5AT1Gb1xkeDS2HNg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736954037; c=relaxed/simple; bh=oKtr2yT6s/jpW26jhtHNEuBn/CVvDww104FyvMi+RVg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Y+UxhQ4jwAl6YY4cC0fFv23Xua6IoiuU3oN6BrswFM9Zpv/WFlly7pyoD8OEx3Y4bVFdv0AaEsqvJtsJMumiN3VMWoAcLrco84ZcuzcKJzFGuj813QJ40JGhPNwwui31xMK++RbVbLhioLee+fvjPsPxY6WVuzDNiIAFjQYU+Is= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PYlBD+ib; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PYlBD+ib" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09926C4CED1; Wed, 15 Jan 2025 15:13:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736954037; bh=oKtr2yT6s/jpW26jhtHNEuBn/CVvDww104FyvMi+RVg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PYlBD+ibBDE3C517s+7YxD2upXox0SGbqHhT/vXqSwXAvK7PFqBnF5F6RJdQMQFe5 1nZ4xEAnTPl+T6rUzP8QtXAQ7rJRdVBe8VKyvquLCzrPQBlqGwvaI+hlqPwuAj5kEN gnIH7u0kId3CaDqIK8J5qtiYV20q0t7qWCrmPz+QQQ6HnAJwLwOLC9zBTOSPjAcJrt Wu90Ko8k2tHRks78HjuiIq6uJpoD8KJyuz2JzXFKY43+bafm08EsFPxKNwd5qskfiV 4HzIQnYHUQrBocaS7/hPa/uV7lMt3+lw8Q3aMkAZ3iLghHpiEf2N+JY89iKYIOJJfJ RpERaWNrId5OA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tY55e-00CWmx-FH; Wed, 15 Jan 2025 15:13:54 +0000 Date: Wed, 15 Jan 2025 15:13:54 +0000 Message-ID: <865xmgw1n1.wl-maz@kernel.org> From: Marc Zyngier To: =?UTF-8?B?TWlrb8WCYWo=?= Lenczewski Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ryan.roberts@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com Subject: Re: [PATCH v1] arm64: Add TLB Conflict Abort Exception handler to KVM In-Reply-To: <20250110172411.39845-3-miko.lenczewski@arm.com> References: <20250110172411.39845-3-miko.lenczewski@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: miko.lenczewski@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ryan.roberts@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 10 Jan 2025 17:24:07 +0000, Miko=C5=82aj Lenczewski wrote: >=20 > Currently, KVM does not handle the case of a stage 2 TLB conflict abort > exception. This can legitimately occurs when the guest is eliding full > BBM semantics as permitted by BBM level 2. In this case it is possible > for a confclit abort to be delivered to EL2. We handle that by > invalidating the full TLB. >=20 > The Arm ARM specifies that the worst-case invalidation is either a > `tlbi vmalls12e1` or a `tlbi alle1` (as per DDI0487K section D8.16.3). > We implement `tlbi alle1` by extending the existing > __kvm_flush_vm_context() helper to allow for differentiating between > inner-shareable and cpu-local invalidations. >=20 > This commit applies on top of v6.13-rc2 (fac04efc5c79). >=20 > Signed-off-by: Miko=C5=82aj Lenczewski > --- > arch/arm64/include/asm/esr.h | 8 ++++++++ > arch/arm64/include/asm/kvm_asm.h | 2 +- > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 2 +- > arch/arm64/kvm/hyp/nvhe/tlb.c | 9 +++++++-- > arch/arm64/kvm/hyp/vhe/tlb.c | 9 +++++++-- > arch/arm64/kvm/mmu.c | 13 +++++++++++++ > arch/arm64/kvm/vmid.c | 2 +- > 7 files changed, 38 insertions(+), 7 deletions(-) > [...] > diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c > index c9d46ad57e52..7c0d97449d23 100644 > --- a/arch/arm64/kvm/mmu.c > +++ b/arch/arm64/kvm/mmu.c > @@ -1756,6 +1756,19 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) > ipa =3D fault_ipa =3D kvm_vcpu_get_fault_ipa(vcpu); > is_iabt =3D kvm_vcpu_trap_is_iabt(vcpu); > =20 > + if (esr_fsc_is_tlb_conflict_abort(esr)) { > + > + /* Architecturely, at this stage 2 tlb conflict abort, we must > + * either perform a `tlbi vmalls12e1`, or a `tlbi alle1`. Due > + * to nesting of VMs, we would have to iterate all flattened > + * VMIDs to clean out a single guest, so we perform a `tlbi alle1` > + * instead to save time. > + */ > + __kvm_flush_vm_context(true); > + > + return 1; > + } > + This is broken. At this stage, you are preemptible, so whatever invalidation you are performing might be happening on the wrong CPU (and I really don't want to see a broadcast invalidation). I really don't see why this can't be handled as a fixup in the inner run loop, which would save *a lot* of cycles and do the right thing. Thanks, M. --=20 Without deviation from the norm, progress is not possible.